S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 54

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product: PCI Configuration Registers
CACHE LINE SIZE REGISTER (CALN)
Figure 13. Cache Line Size Register
AMCC Confidential and Proprietary
Register Name:
Address Offset:
Power-up value:
Boot-load:
Attribute:
Size:
7
Cache Line Size
0Ch
00h, hardwired
not used
Read Only
8 bits
00h
The cache line configuration register is used by bus
masters implementing memory write and invalidate
commands. The register defines the cache line size in
double word (64-bit) increments. The S5920 is a target
device not requiring cache. The register is hardwired
to 0.
Cache Line Size (RO)
Revision 1.02 – April 12, 2007
Data Book
DS1596
0
54