S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 65

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product: PCI Configuration Registers
EXPANSION ROM BASE ADDRESS REG-
ISTER (XROM)
Figure 21. Expansion ROM Base Address Register
AMCC Confidential and Proprietary
Register Name:
Address Offset:
Power-up value:
Boot-load:
Attribute:
Size:
31:11
10:1
31
Bit
0
Expansion ROM Base Address Location. These bits are used to position the decoded region in memory space.
Only bits which return a 1 after being written as 1 are usable for this purpose. These bits are individually enabled
by the contents sourced from the external boot memory (nvRAM). The desired size for the ROM memory is
determined by writing all ones to this register and then reading back the contents. The number of bits returned
as zeros, in order from least significant to most significant bit, indicates the size of the expansion ROM. This
controller limits the expansion ROM area to 2K bytes (due to the serial nvRAM’s limit of 11 bits of address). The
allowable returned values after all ones are written to this register are shown in Table 18.
Reserved. All zeros.
Address Decode Enable. The Expansion ROM address decoder is enabled or disabled with this bit. When this
bit is set, the decoder is enabled. When this bit is cleared, the decoder is disabled. It is required the PCI com-
mand register (PCICMD) also have the memory decode bit enabled for this bit to have any effect. In addition,
the corresponding bit must be set in the external nvRAM (see page 2-74, Table 1). If not set, the PCI host can-
not enable/disable this Address Decode bit.
Expansion ROM Base Address
30h
00000000h
External nvRAM offset 70h
bits 31:11, bit 0 Read/Write; bits 10:1
Read Only
32 bits
11
10
Description
The Expansion ROM Base Address Register provides
a mechanism for assigning a space within physical
memory for a BIOS expansion ROM. Access from the
PCI bus to the memory space defined by this register
will cause one or more accesses to the S5920 external
nvRAM interface. Since PCI bus accesses to the ROM
may be 32 bits wide, repeated read operations to the
ROM are generated, and the wider data is assembled
internal to the S5920 controller. The data is then trans-
ferred to the PCI bus by the S5920. Only memory read
cycles should be performed to this location.
0
1
Revision 1.02 – April 12, 2007
0
0
Bit
Value
Address Decode
Enable (RW)
Reserved (RO)
0 = Disabled
1 = Enabled
Programmable (R/W)
Data Book
DS1596
65