S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 138

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product: Pass-Thru Operation
When the device is programmed for Big Endian trans-
lation and a 32-bit data bus, the S5920 will convert as
described in Table 3.
Active mode is provided to simplify logic requirements
when interfacing an application to the Add-On Local
bus. Passive mode requires Add-On logic to assert
read/write signals and drive or latch data on the DQ
bus.
Strapping PTMODE low configures the S5920 for
Active mode operation. Active mode allows more
designer flexibility through programmable features.
The following is a brief description of these features.
Active Operation
In Active mode, a data transfer start is signaled on the
first clock edge in which PTATN# is sampled low. If
Figure 70. PCI to Add-On Passive Read to an 16-bit Add-On Device
AMCC Confidential and Proprietary
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Pass-Thru address can be driven automatically
at the beginning of all transfers or can be
skipped altogether if addresses are unneeded
by Add-On logic.
Programmed or Add-On controlled wait states
to delay data transfers automatically or on the
fly.
Endian Conversion
Write FIFO ( Write posting )
Read FIFO ( Prefetch )
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
WR#
DQ[31:16]
DQ[15:0]
PTADR#
PTRDY#
ADCLK
0
1
[31:16]
ADDR
ADDR
[15:0]
0h
2
3
LOW
Ch
D1
4
HIGH
3h
3h
D1
3h
5
0h
LOW
Ch
D2
2Ch
6
HIGH
PTADR# has been programmed to be output it will go
active (low) at this time, and the data presented on the
DQ bus is the address for the current transaction. Add-
On logic may latch the address value at the rising
edge of the clock. Address cycles do not count toward
the number of wait states needed to complete data
phases. In Active mode, the PTRDY# pin is renamed
to PTWAIT#. On cycles after PTWAIT# is sampled low,
the state machine is idle. Idle cycles are also not
counted as wait states by the S5920. To control the
number of wait states on an as-needed basis only,
zero wait states should be programmed and PTWAIT#
can be driven low when wait states are to be inserted.
If PTWAIT# is low when PTATN# is asserted by the
S5920, the pending transfer cycle won’t be started
until PTWAIT# is driven high.
Table 56. Showing Big Endian Conversion for 32-bit
3h
3h
D2
Byte#
7
0h
LOW
0
1
2
3
Ch
D3
8
HIGH
3h
3h
D3
9
Fh
PCI Byte
D23-D15
D31-D24
D15-D8
D7-D0
10
Revision 1.02 – April 12, 2007
11
12
Data Book
Add-On Byte
D31-D24
D23-D16
13
D15-D8
D7-D0
DS1596
138