S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 59

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product: PCI Configuration Registers
Figure 17. Base Address Register - Memory
AMCC Confidential and Proprietary
31:4
2:1
Bit
3
2
0
31
x
Base Address Location. These bits locate the decoded region in memory space. Only bits which return a 1 after
being written as 1 are usable for this purpose. Except for Base Address Register 0, these bits are individually
enabled by the contents sourced from the external boot memory.
Prefetchable. When set as a 1, this bit signifies that this region of memory can be cached. Cacheable regions
can only be located within the region altered through PCI bus memory writes. This bit, when set, also implies
that all read operations will return the data associated for all bytes regardless of the Byte Enables. Memory
space which cannot support this behavior should leave this bit in the zero state. this bit is set by the reset pin
and later initialized by the external boot memory option. Base Address Register 0 always has this bit set to 0.
This bit is read only from the PCI interface. This bit has no implementation in the S5920 other than providing it
during a configuration read cycle.
Memory Type. These bits define whether the memory space is 32 or 64 bits wide and if the space location is
restricted to be within the first megabyte of memory space. The encoding is as follows:
Note: The 64-bit memory space is not supported by this device. Bit 2 is hardwired to 0. Options are restricted to
desired to memory space anywhere within 32-bit memory space or located in the first megabyte. For Base
Addresses 1 through 4, this bit is cleared by the reset pin and later initialized by the external boot memory
option.
Space Indicator = 0. When set to 0, this bit defines a base address region as memory space and the remaining
bits in the base address register are defined as shown in Figure 17.
2
0
0
1
1
30
Bits
x
1
0
1
0
1
29
Description
Region is 32-bits wide and can be located anywhere in 32-bit memory space.
Region is 32 bits wide and must be mapped below the first Mbytes of memory space.
Region is 64 bits wide and can be mapped anywhere within 64-bit memory space. (Not supported
by this device.)
Reserved.
Base Address
4
3
0
Description
2
0
1
0
0
0
Bit
Value
Memory Space
Indicator (RO)
Type (RO)
Prefetchable (RO)
Programmable (RO)
D31
0
0
1
1
00 = Locate
Anywhere (32)
01 = Below 1 MB
10 = Locate Anywhere (64)
11 = Reserved
Revision 1.02 – April 12, 2007
D30
0
1
0
1
Add-On Bus Width
Region Disable
8 bits
16 bits
32 bits
Data Book
DS1596
59