S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 86

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product: Operation Registers
Table 46. Interrupt Control Status Register
AMCC Confidential and Proprietary
31:24
22:21
19:18
15:13
11:10
9:8
7:5
3:2
1:0
Bit
23
20
17
16
12
4
Reserved. Always zero.
Interrupt Asserted. This read-only status bit indicates that one or more interrupt conditions are present. This bit
is the OR of the interrupt sources described by bits 20, 17 and 16 of this register.
Reserved. Always zero.
BIST. Built-In Self-Test Interrupt. This interrupt occurs when a self test is initiated by the PCI interface by writing
to the PCI configuration register BIST. This bit will stay set until cleared by writing a 1 to this location. Self test
completion codes may be passed to the PCI BIST register by writing to the ARCR register.
Reserved. Always zero.
Outgoing Mailbox Interrupt. This bit can be set when the mailbox is read by the PCI interface. This bit operates
as read or write 1 clear. A write with the data as 1 will cause this bit to be reset; a write with the data as 0 will not
change the state of this bit.
Incoming Mailbox Interrupt. This bit can be set when the mailbox is written by the PCI interface. This bit oper-
ates as read or write 1 clear. A write with the data as 1 will cause this bit to be reset; a write with the data as 0
will not change the state of this bit.
Reserved. Always zero.
Enable Outgoing Mailbox Interrupt. This bit allows a PCI read of the outgoing mailbox register to produce an
Add-On interrupt. This bit is read/write.
Hardwired to 11.
Outgoing Mailbox Byte Interrupt Select. This field selects which byte of the mailbox is to cause the interrupt.
[00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte 3. This field is read/write.
Reserved. Always zero.
Enable Incoming Mailbox Interrupt. This bit allows a write from the PCI bus to the incoming mailbox register to
produce an Add-On interrupt. This bit is read/write.
Hardwired to 1.
Incoming Mailbox Byte Interrupt Select. This field selects which byte of the mailbox is to cause the interrupt. 00b
selects byte 0, 01b selects byte 2, and 11b selects byte 3. This field is read/write.
Description
Revision 1.02 – April 12, 2007
Data Book
DS1596
86