S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 111

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product: Mailbox Overview
Figure 56. Add-On to PCI Mailbox Register
Mailbox Empty/Full Conditions
The PCI and Add-On interfaces each have a mailbox
status register. The PCI Mailbox Empty/Full Status
(MBEF) and Add-On Mailbox Empty/Full Status
(AMBEF) registers indicate the status of all bytes
within the mailbox registers. A write to an outgoing
mailbox sets the status bits for that mailbox. The byte
enables determine which bytes within the mailbox
become full (and which status bits are set).
An outgoing mailbox for one interface is an incoming
mailbox for the other. Therefore, incoming mailbox sta-
t u s b i ts o n o n e i n t e r f a c e a r e i d e n t i c a l t o t h e
corresponding outgoing mailbox status bits on the
other interface. The following list shows the relation-
ship between the mailbox registers on the PCI and
Add-On interfaces.
A write to an outgoing mailbox also writes data into the
incoming mailbox on the other interface. It also sets
the status bits for the outgoing mailbox and the status
bits for the incoming mailbox on the other interface.
Reading the incoming mailbox clears the correspond-
ing status bit(s) in the Add-On and PCI mailbox status
registers (AMBEF and MBEF).
For example, a PCI write is performed to the PCI out-
going mailbox, writing bytes 0 and 1 (CBE0# and
CBE1# asserted). Reading the PCI Mailbox Empty/
Full Status Register (MBEF) indicates that bits 12 and
AMCC Confidential and Proprietary
PCI Interface
Outgoing Mailbox
Incoming Mailbox
PCI Mailbox Empty/
Full
PCI BUS
PCI READ
PCI CLK
=
=
=
Add-On Interface
Full
INTERLOCK
Incoming Mailbox
Outgoing Mailbox
Add-On Mailbox Empty/
REGISTER
OUTPUT
Q
EN
D
ADCLK
V
DD
INCOMMING
D
MAILBOX
R
S
PCI
Q
ADCLK
MAILBOX
13 are set. These bits indicate that outgoing mailbox
bytes 0 and 1 are full. Reading the Add-On Mailbox
Empty/Full Status Register (AMBEF) shows that bits
12 and 13 in this register are also set, indicating the
Add-On incoming mailbox bytes 0 and 1 are full. An
Add-On read of the incoming mailbox, bytes 0 and 1,
clears the status bits in both the MBEF and AMBEF
status registers.
The read-only status flags in the MBEF and AMBEF
registers are reset when the corresponding byte is
read from the incoming mailbox. Alternately, these
flags can be globally reset from either the PCI inter-
face or the Add-On interface. The PCI Bus Reset
Control Register (RCR) and the Add-On Reset Control
Register (ARCR) each have a bit to reset all of the
mailbox status flags.
Mailbox Interrupts
The designer has the option to generate interrupts to
the PCI and Add-On interfaces when specific mailbox
events occur. The PCI and Add-On interfaces can
each define two conditions where interrupts may be
generated. An interrupt can be generated when the
incoming mailbox becomes full and/or when the outgo-
ing mailbox becomes empty. A specific byte within a
specific mailbox is selected to generate the interrupt.
The conditions defined to generate interrupts to the
PCI interface do not have to be the same as the condi-
tions defined for the Add-On interface.
For the incoming mailbox interrupts, when the speci-
fied byte becomes full, an interrupt is generated. The
interrupt might be used to indicate command or status
information has been provided, and must be read. For
FULL
REGISTER
MAILBOX
Q
EN
Q
EN
D
D
ADD-ON BUS
ADCLK
Revision 1.02 – April 12, 2007
WR#
SELECT#
ADR -MB
Data Book
DS1596
111