S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 6

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product
PCI READ TRANSFERS ..................................................................................................................................... 104
PCI WRITE TRANSFERS ................................................................................................................................... 104
PCI BUS INTERRUPTS ...................................................................................................................................... 108
PCI BUS PARITY ERRORS ................................................................................................................................ 108
MAILBOX OVERVIEW ........................................................................................................................................ 110
FUNCTIONAL DESCRIPTION ............................................................................................................................ 110
BUS INTERFACE ................................................................................................................................................ 112
CONFIGURATION ............................................................................................................................................... 113
ADD-ON LOCAL BUS INTERFACE ................................................................................................................... 118
ADD-ON INTERFACE SIGNALS ........................................................................................................................ 118
SYSTEM SIGNALS ............................................................................................................................................. 118
ADD-ON S5920 REGISTER ACCESSES ........................................................................................................... 118
AMCC Confidential and Proprietary
Single Data Phase PCI Bus Read of S5920 Registers or Expansion ROM .................................................. 104
Burst PCI Bus Read Attempt to S5920 Registers or Expansion ROM .......................................................... 104
Burst PCI Bus Write of S5920 Registers ....................................................................................................... 105
Target-Initiated Termination .......................................................................................................................... 105
Target Disconnects ........................................................................................................................................ 105
Target Requested Retries ............................................................................................................................. 105
Figure 4a. Target Disconnect Example 1 ...................................................................................................... 105
Figure 4b. Target Disconnect Example 2 ...................................................................................................... 105
Target Aborts ................................................................................................................................................. 105
Target Latency ............................................................................................................................................... 106
Target Locking ............................................................................................................................................... 106
PCI Bus Access Latency Components .......................................................................................................... 106
Figure 5. Target-Initiated Retry ...................................................................................................................... 106
Figure 6. Engaging the LOCK# Signal .......................................................................................................... 106
Target Termination Type ............................................................................................................................... 107
Access to a Locked Target by its Owner ....................................................................................................... 109
Access Attempt to a Locked Target ............................................................................................................... 109
Error Reporting Signal ................................................................................................................................... 109
Figure 1. PCI to Add-On Mailbox Register .................................................................................................... 110
Add-On to PCI Mailbox Register ................................................................................................................... 111
Mailbox Empty/Full Conditions ...................................................................................................................... 111
Mailbox Interrupts .......................................................................................................................................... 111
Add-On Outgoing Mailbox, Byte 3 Access .................................................................................................... 112
PCI Bus Interface .......................................................................................................................................... 112
Add-On Bus Interface .................................................................................................................................... 112
8-Bit and 16-Bit Add-On Interfaces ................................................................................................................ 113
Mailbox Status ............................................................................................................................................... 113
Input/Output Mode (MDMODE=0) ................................................................................................................. 113
Input Mode (MDMODE=1) ............................................................................................................................. 113
Mailbox Interrupts .......................................................................................................................................... 115
Servicing a PCI Mailbox Interrupt (INTA# asserted): ..................................................................................... 116
Register Access Signals ................................................................................................................................ 118
S5920 General Register Accesses ................................................................................................................ 118
Read Operation Register ............................................................................................................................... 119
Write Operation Register ............................................................................................................................... 119
Revision 1.02 – April 12, 2007
Data Book
DS1596
6