S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 112

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product: Mailbox Overview
PCI incoming mailbox interrupts, the S5920 asserts
the PCI interrupt, INTA#. For Add-On incoming mail-
box interrupts, the S5920 asserts the Add-On
interrupt, IRQ#.
For the outgoing mailbox interrupts, when the speci-
fied byte becomes empty, an interrupt is generated.
The interrupt might be used to indicate that the other
interface has received the last information sent and
more may be written. For PCI outgoing mailbox inter-
rupts, the S5920 asserts the PCI interrupt, INTA#. For
Add-On outgoing mailbox interrupts, the S5920
asserts the Add-On interrupt, IRQ#.
Add-On Outgoing Mailbox, Byte 3 Access
PCI incoming mailbox byte 3 (Add-On outgoing mail-
box, byte 3, or AOMB[3]) has been further enhanced
by the addition of a separate 8-bit interface (MD[7:0])
on the Add-On side. This interface can be used to
write to AOMB[3] instead of/or in addition to the nor-
mal method (via an Add-On Operation Register write
to AOMB[3]).
The MD[7:0] bus can be configured in one of two
modes: Input mode or I/O mode. If the configuration
pin MDMODE is strapped high, the MD[7:0] bus is set
to be in input mode only. If MDMODE is strapped low,
the MD[7:0] bus will operate in a bi-directional mode. If
the MD[7:0] bus is set up for input-only mode, data will
be latched into AOMB[3] when the LOAD# input is
sampled low by the Add-On clock. The LOAD# input
pin may also be used to generate a PCI interrupt if the
appropriate interrupt is enabled in the Interrupt Con-
trol/Status Register (INTCSR). These functions are
identical to the Add-On device writing to its byte 3 out-
going mailbox via the DQ bus. As a matter of fact,
Add-On mailbox byte 3 is accessible by either the
external mailbox port or the Add-On interface. Which-
ever interface writes to it last will determine the data
that resides in that register.
AMCC Confidential and Proprietary
Signal Pin
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
Add-On Outgoing Mailbox
Mailbox, Bit 25
Mailbox, Bit 26
Mailbox, Bit 27
Mailbox, Bit 28
Mailbox, Bit 30
Mailbox, Bit 31
Mailbox,Bit 24
Mailbox,Bit 29
When the MD[7:0] bus is set up for I/O mode and
LOAD# is high (deasserted), the MD[7:0] bus is an
active output, driving the contents of the PCI outgoing
mailbox, byte 3 (OMB[3]). In this case, the MD[7:0]
bus will be updated anytime the PCI writes to mailbox
OMB[3]. As a result, the MD[7:0] bus will be synchro-
nous to the PCI clock. When LOAD# is driven low, the
MD[7:0] bus is tri-stated, allowing external data to be
latched into Add-On outgoing mailbox byte 3. This is a
similar function that exists for input-only.
Figures 3 and 4 show the interaction between the
MD[7:0] bus and the LOAD# input pin. Note that a
turnaround cycle is utilized when writing data to the
mailbox byte in I/O mode. This is to prevent contention
on the MD[7:0] drivers.
BUS INTERFACE
The mailboxes appear on the Add-On and PCI bus
interfaces as two operation registers. One is the out-
going mailbox, and the other is the incoming mailbox.
These mailboxes may be used to generate interrupts
to each of the interfaces. The following sections
describe the Add-On and PCI bus interfaces for the
mailbox registers.
PCI Bus Interface
The mailbox operation registers do not support burst
accesses by an initiator. A PCI initiator attempting to
burst to the mailbox registers causes the S5920 to
respond with a target disconnect with data. PCI writes
to a full outgoing mailbox overwrite data currently in
that mailbox. PCI reads from an empty incoming mail-
box return the data that was previously contained in
the mailbox. In this case, the data cannot be guaran-
teed. It is intended for the user to verify that a mailbox
is full before it is read.
PCI incoming and outgoing mailbox interrupts are
enabled/disabled in the INTCSR. The mailboxes can
generate a PCI interrupt (INTA#) under two conditions
(individually enabled). For an incoming mailbox full
interrupt, INTA# is asserted on the rising edge of the
PCI clock after the Add-On mailbox write completes.
For an outgoing mailbox empty interrupt, INTA# is
asserted on the rising edge of the PCI clock after the
Add-On mailbox read completes. INTA# is deasserted
one PCI clock cycle after the mailbox interrupt is ser-
viced (by writing a 1 to the proper interrupt source bit).
Add-On Bus Interface
The Add-On mailbox interface behaves similarly to the
PCI bus interface. Add-On writes to a full outgoing
mailbox overwrite data currently in that mailbox. PCI
reads from an empty incoming mailbox return the data
that was previously contained in the mailbox.
Revision 1.02 – April 12, 2007
Data Book
DS1596
112