S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 82

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product: Operation Registers
ADD-ON INCOMING MAILBOX REGISTER (AIMB)
ADD-ON OUTGOING MAILBOX REGISTER (AOMB)
ADD-ON PASS-THRU ADDRESS REGISTER (APTA)
ADD-ON PASS-THRU DATA REGISTER (APTD)
AMCC Confidential and Proprietary
Register Names:
Add-On Address:
Power-up value:
Add-On Attribute:
Size:
Register Names:
Add-On Address:
Power-up value:
Add-On Attribute:
Size:
Register Name:
Add-On Address:
Power-up value:
Add-On Attribute:
Size:
Register Name:
Add-On Address:
Power-up value:
Add-On Attribute:
Size:
Incoming Mailbox
0Ch
XXXXXXXXh
Read Only
32 bits
Outgoing Mailbox
1Ch
XXXXXXXXh
Read/Write
32 bits
Add-On Pass-Thru Address
28h
XXXXXXXXh
Read Only
32 bits
Add-On Pass-Thru Data
2Ch
XXXXXXXXh
Read/Write
32 bits
This DWORD register provides a method for receiving user-defined status or
parameter data from the PCI system. Add-On bus read operations to this register
may be of any width (byte, word, or DWORD). Only read operations are sup-
ported. Reading from this register can optionally cause a PCI bus interrupt (if
desired) by enabling interrupt generation through the use of the PCI’s Interrupt
Control/Status Register. This register is also referred to as the PCI Outgoing Mail-
box Register.
This DWORD register provides a method for sending command or parameter
data to the PCI interface. Add-On bus operations to this register may be of any
width (byte, word, or DWORD). Writing to this register can be a source for PCI
bus interrupts (if desired) by enabling interrupt generation through the use of the
PCI’s Interrupt Control/Status Register. This is also called the PCI Incoming Mail-
box Register (IMB). Byte 3 of this mailbox can also be controlled via the external
mailbox port. Reading from this register will not affect interrupts or the AMBEF
Status Register. (OMB).
This register, along with APTA register, is used to perform Pass-Thru
transfers. When one of the base address decode registers 1-4 encounters
a PCI bus cycle which selects the region defined by it, the APTA register
will contain that current cycle’s active address and the APTD will contain
the data (PCI bus writes) or must be written with data (PCI bus reads).
Wait states are generated on the PCI bus until this register is read (PCI
bus writes) or this register is written (PCI bus reads) when in Passive
mode.
This register stores the address of any active Pass-Thru PCI bus cycle
that has been accepted by the S5920. When one of the base address
decode registers 1-4 encounters a PCI bus cycle which selects the
region defined by it, this register stores that current cycle’s active
address. This address is incremented after every 32-bit Pass-Thru data
transfer.
Revision 1.02 – April 12, 2007
Data Book
DS1596
82