S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet
S5920Q
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S5920Q Summary of contents
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S5920 PCI Product AMCC Confidential and Proprietary S5920 PCI PRODUCT Part Number S5920 Revision 1.02 – April 12, 2007 Data Sheet DS1596 1 ...
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S5920 – PCI Product VISION ................................................................................................................................................................... 14 CORPORATE OVERVIEW .................................................................................................................................... 14 AMCC Product Development Strategy ............................................................................................................ 14 Network Interface Products ............................................................................................................................. 14 AMCC Product Development Strategy ............................................................................................................ 14 Peripheral Component Interconnect (PCI) Bus Controllers ............................................................................. 15 Precision Clock and Timing ...
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S5920 – PCI Product S5920 REGISTER ARCHITECTURE .................................................................................................................... 28 PCI Configuration Registers ............................................................................................................................ 28 PCI Bus Accessible Registers ......................................................................................................................... 28 Add-On Bus Accessible Registers ................................................................................................................... 28 SERIAL NON-VOLATILE INTERFACE ................................................................................................................ 28 S5920 Pinout ................................................................................................................................................... 29 MAILBOX OPERATION ........................................................................................................................................ 30 PASS-THRU ...
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S5920 – PCI Product Base Class Code 0Bh: Processors ................................................................................................................. 53 Base Class Code 0Ch: Serial Bus Controllers ................................................................................................ 53 CACHE LINE SIZE REGISTER (CALN) ............................................................................................................... 54 Cache Line Size Register ................................................................................................................................ 54 LATENCY TIMER REGISTER (LAT) .................................................................................................................... 55 Latency ...
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S5920 – PCI Product FIFO Control/Status Register .......................................................................................................................... 77 Reset Control Register .................................................................................................................................... 78 PCI PASS-THRU CONFIGURATION REGISTER (PTCR) ................................................................................... 79 Pass-Thru Configuration Register ................................................................................................................... 79 ......................................................................................................................................................................... 80 ADD-ON BUS OPERATION REGISTERS ............................................................................................................ 81 Operation Registers - Add-On Interface .......................................................................................................... ...
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S5920 – PCI Product PCI READ TRANSFERS ..................................................................................................................................... 104 Single Data Phase PCI Bus Read of S5920 Registers or Expansion ROM .................................................. 104 PCI WRITE TRANSFERS ................................................................................................................................... 104 Burst PCI Bus Read Attempt to S5920 Registers or Expansion ROM .......................................................... ...
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S5920 – PCI Product S5920 16-bit Mode Register Accesses ......................................................................................................... 119 16 Bit Mode Operation Register DWORD Write/Read .................................................................................. 120 MAILBOX OVERVIEW ........................................................................................................................................ 121 PASS-THRU OVERVIEW .................................................................................................................................... 121 WRITE FIFO OVERVIEW .................................................................................................................................... 121 FUNCTIONAL DESCRIPTION ............................................................................................................................ 121 Pass-Thru Transfers ...................................................................................................................................... ...
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S5920 – PCI Product Active mode Burst cycles .............................................................................................................................. 141 Active Mode 32-Bit PCI Write w/PTWAIT# .................................................................................................... 142 Clock by Clock description of Figure 16 ........................................................................................................ 142 Clock by Clock description of Figure 17 ........................................................................................................ 143 Active Mode PCI Write ...
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S5920 – PCI Product Figure 1. AMCC Product Development Strategy ................................................................................................... 14 Figure 2. S5920 Block Diagram ............................................................................................................................. 27 Figure 3. S5920 Pinout .......................................................................................................................................... 29 Figure 4. Mailbox Block Diagram ........................................................................................................................... 30 Figure 5. Pass-Thru Block Diagram ....................................................................................................................... 31 Figure ...
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S5920 – PCI Product Figure 42. PCI AD Bus Definition Type 0 Configuration Access ............................................................................ 98 Figure 43. Type 0 Configuration Read Cycles ....................................................................................................... 98 Figure 44. Type 0 Configuration Write Cycles ....................................................................................................... 99 Figure 45. Single Data Phase PCI ...
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S5920 – PCI Product Figure 83. PCI Clock Timing ................................................................................................................................ 152 Figure 84. PCI Signal Output Timing ................................................................................................................... 153 Figure 85. PCI Signal Input Timing ...................................................................................................................... 153 Figure 86. Add-On Clock Timing .......................................................................................................................... 156 Figure 87. Pass-Thru Clock Relationship to ...
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S5920 – PCI Product Table 1. ATM LAN and 100VG AnyLAN Products ................................................................................................. 22 Table 2. Fibre Channel/Gigabit Ethernet Products ................................................................................................ 22 Table 4. PCI Products ............................................................................................................................................ 23 Table 5. SONET/SDH/ATM Products .................................................................................................................... 23 Table 3. HIPPI Products ........................................................................................................................................ 23 ...
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S5920 – PCI Product Table 42. Reset Control Register ........................................................................................................................... 78 Table 43. ............................................................................................................................................................... 80 Table 44. Operation Registers - Add-On Interface ................................................................................................ 81 Table 45. Mailbox Empty/Full Status Register ....................................................................................................... 84 Table 46. Interrupt Control Status Register ........................................................................................................... 86 ...
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S5920 – PCI Product: Capability Summary VISION It is AMCC’s vision to be the premier supplier of silicon for high bandwidth connectivity solutions for the world- wide networking infrastructure. CORPORATE OVERVIEW AMCC defines, develops, manufactures and markets application specific standard ...
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S5920 – PCI Product: Capability Summary AMCC interface circuits, transceiver chips and switches are designed to implement emerging network technologies such as the ANSI Fibre Channel and High Performance Interface (HIPPI) standards, the ITU SONET telecommunications standard, the ATM Forum ...
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S5920 – PCI Product: Quality System Overview AMCC COMMITMENT TO QUALITY AMCC is committed to achieving the highest quality and reliability level in the integrated circuit products we provide. Every year for over a decade we have estab- lished industry-leading ...
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S5920 – PCI Product: Quality System Overview Continuous Quality Improvement Program • Corporate-wide commitment driven by the Executive Staff • A program plan that is flexible enough to com- prehend dynamic customer inputs • Statistical tools in place for analysis ...
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S5920 – PCI Product: Quality System Overview PRODUCT QUALIFICATIONS A qualification is a sequence of tests in which all parameters, including the reliability of the device are tested this sequence of tests which initially qual- ifies the part ...
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S5920 – PCI Product: Quality System Overview Design For Manufacturability And Reliability Incoming Inspection Wafer Fabrication Wafer Electrical Test Wafer Stores AMCC Confidential and Proprietary Revision 1.01 – September 21, 2005 AMCC Product Assurance Product Flow Detail • Component Selection ...
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S5920 – PCI Product: Quality System Overview AMCC Product Assurance Product Flow Detail Assembly Issue Assembly and Environmental Screening Pre-Electrical and Burn-In Final Electrical Test Group B Group C & D CSI Packaging for Shipment Ship 1. MIL-H-38534 or MIL-STD-883 ...
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S5920 – PCI Product: Quality System Overview AMCC’S RELIABILITY VIGIL AMCC’s internal reliability vigil consists of three phases: • New/changed processes and material qualifi- cations • In-process Quality monitors • Periodic operating life and environmental test- ing New/Changed Wafer Processes ...
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S5920 – PCI Product: Product Selection Guides Table 1. ATM LAN and 100VG AnyLAN Products Products Function S3011 SONET/ATM/ E-4 Tx S3012 SONET/ATM/ E-4 Rx S3020 ATM Tx S3021 ATM Rx S3027 Clock Recovery S3028 ATM Transceiver S3029 Quad Transceiver ...
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S5920 – PCI Product: Product Selection Guides Table 3. HIPPI Products Products Function S2020 HIPPI Source S2021 HIPPI Destination See Network Products data book or http://www.amcc.com. Table 4. PCI Products Products Function S5920 Target PCI Interface S5920DK1 Developer's Kit S5933 ...
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S5920 – PCI Product: Product Selection Guides Table 6. SONET/SDH/ATM Products (continued) Products Function S3040 SONET/SDH Clock Recovery Unit S3041 SONET/SDH Transmitter S3042 SONET/SDH Demux S3043 SONET/SDH Transmitter S3044 SONET/SDH Demux S3045 SONET/SDH OC-12 to OC-48 S3047 SONET/SDH Clock and ...
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S5920 – PCI Product: Product Selection Guides Table 9. Clock Generator and Synthesizer Products Output Frequency with Respect to Input Frequency P/N Description Reference S4402 Multiphase Clock Generator 4403 Multiphase Clock Generator 4405 Multiphase Clock PECL/TTL Generator S4406 Clock Generator ...
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S5920 – PCI Product: Product Selection Guides Table 11. ASIC Logic Array Products Part Number Technology Equivalent Gates (Full Adder Method) Q20004 1 Micron Bipolar Q20010 1 Micron Bipolar Q20025 1 Micron Bipolar Q20045 1 Micron Bipolar Q20080 1 Micron ...
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S5920 – PCI Product: Architectural Overview FEATURES • Full 132 Mbytes/sec Transfer Rate • PCI Bus Operation to 33 MHz • PCI Purposed 2.2 Compliant Target/Slave Device • Add-On Bus MHz • Programmable Prefetch and Wait States ...
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S5920 – PCI Product: Architectural Overview ARCHITECTURAL OVERVIEW S5920 Since the S5920 is a PCI Target or Slave device only, its cost is significantly less than PCI Bus Master solu- tions. The S5920 is PCI purposed 2.2 compliant and can ...
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S5920 – PCI Product: Architectural Overview Figure 3. S5920 Pinout PCLK INTA# RST# AD[31:0] C/BE[3:0]# FRAME# DEVSEL# IRDY# TRDY# IDSEL# STOP# LOCK# PAR PERR# SERR# S5920 FLT# Control AMCC Confidential and Proprietary S5920 BPCLK ADCLK SYSRST# IRQ# ADDINT# DQ[31:0] SELECT# ...
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S5920 – PCI Product: Architectural Overview MAILBOX OPERATION The mailbox registers are divided into two 4-byte sets. Each set is dedicated to one bus for data transfer to the other bus. Figure 3 shows a block diagram of the mailbox ...
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S5920 – PCI Product: Architectural Overview To increase data throughput, the Pass-Thru channel incorporates two 32-byte FIFOs. One FIFO is dedi- cated to PCI read data while the other is dedicated to PCI write data. Enabling the write FIFO allows ...
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S5920 – PCI Product: Signal Description Signal Type Definitions The following signal types are taken from the PCI Bus Specification. in Input is a standard input-only signal. out Totem Pole Output is a standard active driver. t/s Tri-State ®is a ...
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S5920 – PCI Product: Signal Description Figure 6. S5920 Pin Assignment 158 156 155 154 152 ...
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S5920 – PCI Product: Signal Description PCI BUS SIGNALS The following sets of signals represent the interface pins available for the S5920 to PCI bus. Table 12. PCI Bus Address and Data Signal Signal Type AD[31:0] t/s Address/Data. Address and ...
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S5920 – PCI Product: Signal Description Table 13. PCI Bus System Signals Signal Type PCLK in PCI Clock. The rising edge of this signal is the reference upon which all other signals are based except for RST# and INTA#. The ...
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S5920 – PCI Product: Signal Description ADD-ON BUS AND S5920 CONTROL SIGNALS The following sets of signals represent the interface signals available for the user Add-On bus and S5920 control. Table 16. Serial nvRAM Interface Signals Signal Type SCL o/d-out ...
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S5920 – PCI Product: Signal Description USER ADD-ON BUS PIN DESCRIPTIONS The following sets of signals represent the interface pins available for the Add-On bus. The following defines three signal groups: S5920 register access signals, Pass-Thru channel signals, and general ...
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S5920 – PCI Product: Signal Description Table 19. S5920 Add-On Bus Register Access Pins Signal Type DQ[31:0] t/s Address/Data bus. The 32-bit Add-On data bus. The DQMODE signal configures the bus width for either bits. All DQ[31:0] ...
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S5920 – PCI Product: Signal Description Table 20. Add-On Bus General Pins Signal Type SYSRST# out System Reset. An active-low buffered PCI bus RST# output signal. The signal is asynchro- nous and can be asserted through software from the PCI ...
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S5920 – PCI Product: PCI Configuration Registers Each PCI bus device contains a unique 256-byte region called its configuration header space. Portions of this con- figuration header are mandatory in order for a PCI agent full compliance ...
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S5920 – PCI Product: PCI Configuration Registers PCI Configuration Space Header DEVICE ID STATUS BIST SUBSYSTEM ID MAX_LAT LEGEND EPROM IS DATA SOURCE (READ ONLY) CONTROL FUNCTION EPROM INITIALIZED RAM (CAN BE ALTERED FROM PCI PORT) EPROM ...
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S5920 – PCI Product: PCI Configuration Registers VENDOR IDENTIFICATION REGISTER (VID) Vendor Identification Register Name: 00h-01h Address Offset: 10E8h (AMCC’s) Power-up value: External nvRAM offset 040h-41h Boot-load: Read Only Attribute: 16 Bits Size: Figure 7. Vendor Identification Register 15 Bit ...
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S5920 – PCI Product: PCI Configuration Registers DEVICE IDENTIFICATION REGISTER (DID) Device Identification Register Name: 02h-03h Address Offset: 5920h Power-up value: External nvRAM offset 042h-43h Boot-load: Read Only Attribute: 16 bits Size: Figure 8. Device Identification Register 15 Bit 15.0 ...
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S5920 – PCI Product: PCI Configuration Registers PCI COMMAND REGISTER (PCICMD) PCI Command Register Name: 04h-05h Address Offset: 0000h Power-up value: not used Boot-load: Read/Write (R bits, R/O for Attribute: all others) 16 bits Size: Figure 9. PCI ...
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S5920 – PCI Product: PCI Configuration Registers Bit 15:10 Reserved. Hardwired Fast Back-to-Back Enable. This bit enables fast back-to-back capability for bus master transaction. The S5920 is a target-only device and hardwires this bit ...
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S5920 – PCI Product: PCI Configuration Registers PCI STATUS REGISTER (PCISTS) PCI Status Register Name: 06h-07h Address Offset: 0200h Power-up value: not used Boot-load: Read Only Read/Write Clear Attribute: 16 bits Size: Figure 10. PCI Status Register ...
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S5920 – PCI Product: PCI Configuration Registers Bit 15 Detected Parity Error. This bit is set whenever the S5920 detects a parity error set independent of the state of Command Register Bit 6. The bit is cleared by ...
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S5920 – PCI Product: PCI Configuration Registers REVISION IDENTIFICATION REGISTER (RID) Revision Identification Register Name: 08h Address Offset: 00h Power-up value: External nvRAM/EPROM offset Boot-load: 048h R/W Attribute: 8 Bits Size: Figure 11. Revision Identification Register 7 Bit 7:0 Revision ...
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S5920 – PCI Product: PCI Configuration Registers CLASS CODE REGISTER (CLCD) Class Code Register Name: 09h-0Bh Address Offset: FF0000h Power-up value: External nvRAM offset 049h-4Bh Boot-load: Read Only Attribute: 24 Bits Size: Figure 12. Class Code Register @0Bh 7 Base ...
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S5920 – PCI Product: PCI Configuration Registers Table 22. Defined Base Class Codes Base-Class 00h Early, pre-2.0 PCI specification devices 01h Mass storage controller 02h Network controller 03h Display controllers 04h Multimedia devices 05h Memory controllers 06h Bridge devices 07h ...
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S5920 – PCI Product: PCI Configuration Registers Table 25. Base Class Code 02h: Network Controllers Sub-Class Prog I/F 01h 00h Token ring controller 02h 00h FDDI controller 03h 00h ATM controller 80h 00h Other network controller Table 26. Base Class ...
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S5920 – PCI Product: PCI Configuration Registers Table 29. Base Class Code 06h: Bridge Devices Sub-Class 00h 01h 02h 03h 04h 05h 06h 07h 80h Table 30. Base Class Code 07h: Simple Communications Controllers Sub-Class Prog I/F 00h 00h 01h ...
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S5920 – PCI Product: PCI Configuration Registers Table 32. Base Class Code 09h: Input Devices Sub-Class 00h 01h 02h 80h Table 33. Base Class Code 0Ah: Docking Stations Sub-Class 00h 01h 02h 10h 40h Table 34. Base Class Code 0Bh: ...
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S5920 – PCI Product: PCI Configuration Registers CACHE LINE SIZE REGISTER (CALN) Cache Line Size Register Name: 0Ch Address Offset: 00h, hardwired Power-up value: not used Boot-load: Read Only Attribute: 8 bits Size: Figure 13. Cache Line Size Register 7 ...
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S5920 – PCI Product: PCI Configuration Registers LATENCY TIMER REGISTER (LAT) Latency Timer Register Name: 0Dh Address Offset: 00h Power-up value: not used Boot-load: Read Only Attribute: 8 bits Size: Figure 14. Latency Timer Register 7 AMCC Confidential and Proprietary ...
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S5920 – PCI Product: PCI Configuration Registers HEADER TYPE REGISTER (HDR) Header Type Address Offset 0Eh Register Name: 00h, Hardwired Boot-load: External Power-up value: nvRAM offset 04Eh Read Only Attribute: 8 bits Size: Figure 15. Header Type Register 6 7 ...
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S5920 – PCI Product: PCI Configuration Registers BUILT-IN SELF-TEST REGISTER (BIST) Built-in Self-Test Address Offset 0Fh Register Name: 00h Power-up value: External nvRAM/EPROM offset Boot-load: 04Fh D7, D5-0 Read Only PCI bus Attribute: write only 8 bits Size: ...
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S5920 – PCI Product: PCI Configuration Registers BASE ADDRESS REGISTER (BADR) Base Address Register Name: 10h, 14h, 18h, 1Ch, 20h Address Offset: FFFFFF81h for offset 10h; Power-up value: 00000000h for all others External nvRAM offset 050h, 54h, Boot-load: 58h, 5Ch, ...
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S5920 – PCI Product: PCI Configuration Registers Figure 17. Base Address Register - Memory Base Address Bit 31:4 Base Address Location. These bits locate the decoded region in memory space. Only bits which return a ...
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S5920 – PCI Product: PCI Configuration Registers Figure 18. Base Address Register - I/O 31 Base Address Bit 31:2 Base Address Location. These bits are used to position the decoded region in I/O space. Only bits which return a 1 ...
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S5920 – PCI Product: PCI Configuration Registers Table 36. Base Address Register Response (Memory Assigned) to All-Ones Write Operation Response 00000000h none - disabled FFFFFFF0h 16 bytes (4 DWORDs) FFFFFFE0h 32 bytes (8 DWORDs) FFFFFFC0h 64 bytes (16 DWORDs) FFFFFF80h ...
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S5920 – PCI Product: PCI Configuration Registers Table 37. Read Response (I/O Assigned All-Ones Write Operation to a Base Address Register Response 00000000h none - disabled FFFFFFFDh 4 bytes (1 DWORDs) FFFFFFF9h 8 bytes (2 DWORDs) FFFFFFF1h 16 ...
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S5920 – PCI Product: PCI Configuration Registers SUBSYSTEM VENDOR IDENTIFICATION REGISTER (SVID) Subsystem Vendor ID Register Name: 2Ch-2Dh Address Offset: 0000h Power-up value: External nvRAM offset 6Ch-6Dh Boot-load: Read Only (RO) Attribute: 16 bits Size: Figure 19. Subsystem Vendor Identification ...
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S5920 – PCI Product: PCI Configuration Registers SUBSYSTEM ID REGISTER (SID) Subsystem Identification Register Name: 2Eh-2Fh Address Offset: 0000h Power-up value: External nvRAM offset 6Eh-6Fh Boot-load: Read Only (RO) Attribute: 16 bit Size: Figure 20. Subsystem Identification Register 15 Bit ...
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S5920 – PCI Product: PCI Configuration Registers EXPANSION ROM BASE ADDRESS REG- ISTER (XROM) Expansion ROM Base Address Register Name: 30h Address Offset: 00000000h Power-up value: External nvRAM offset 70h Boot-load: bits 31:11, bit 0 Read/Write; bits 10:1 Attribute: Read ...
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S5920 – PCI Product: PCI Configuration Registers Table 38. Read Response to Expansion ROM Base Address Register (after all ones written) Response 00000000h FFFFF801h 2K bytes (512 DWORDs) 1. The Expansion ROM Base Address Register nvRAM boot value is internally ...
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S5920 – PCI Product: PCI Configuration Registers INTERRUPT LINE REGISTER (INTLN) Interrupt Line Register Name: 3Ch Address Offset: FFh Power-up value: External nvRAM offset 7Ch Boot-load: Read/Write Attribute: 8 bits Size: Figure 22. Interrupt Line Register 7 AMCC Confidential and ...
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S5920 – PCI Product: PCI Configuration Registers INTERRUPT PIN REGISTER (INTPIN) Interrupt Pin Register Name: 3Dh Address Offset: 01h Power-up value: External nvRAM offset 7Dh Boot-load: Read Only Attribute: 8 bits Size: Figure 23. Interrupt Pin Register 7 AMCC Confidential ...
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S5920 – PCI Product: PCI Configuration Registers MINIMUM GRANT REGISTER (MINGNT) Minimum Grant Register Name: 3Eh Address Offset: 00h, hardwired Power-up value: not used Boot-load: Read Only Attribute: 8 bits Size: Figure 24. Minimum Grant Register 7 AMCC Confidential and ...
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S5920 – PCI Product: PCI Configuration Registers MAXIMUM LATENCY REGISTER (MAX- LAT) Maximum Latency Register Name: 3Fh Address Offset: 00h, hardwired Power-up value: not used Boot-load: Read Only Attribute: 8 bits Size: Figure 25. Maximum Latency Register 7 AMCC Confidential ...
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S5920 – PCI Product: Operation Registers OPERATION REGISTERS All S5920 control and communications are performed through two register groups: PCI Operation Registers Add-On Operation Registers. Some registers in both groups are accessible from both buses. This chapter describes the PCI ...
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S5920 – PCI Product: Operation Registers OUTGOING MAILBOX REGISTER (OMB) Outgoing Mailbox Register Names: 0Ch PCI Address Offset: Undefined Power-up value: Read/Write PCI Attribute: 32 bits Size: Figure 26. Outgoing Mailbox Byte 3 AMCC Confidential and Proprietary ...
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S5920 – PCI Product: Operation Registers PCI INCOMING MAILBOX REGISTER (IMB) Incoming Mailbox Register Names: 1Ch PCI Address Offset: Undefined Power-up value: Read Only PCI Attribute: 32 bits Size: Figure 27. Incoming Mailbox Byte 3 AMCC Confidential ...
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S5920 – PCI Product: Operation Registers PCI MAILBOX EMPTY/FULL STATUS REG- ISTER (MBEF) Mailbox Empty/Full Status Register Name: 34h PCI Address Offset: 00000000h Power-up value: Read Only PCI Attribute: 32 bits Size: Figure 28. Mailbox Empty/Full Status Register (MBEF) 31 ...
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S5920 – PCI Product: Operation Registers PCI INTERRUPT CONTROL/STATUS REG- ISTER (INTCSR) Interrupt Control and Status Register Name: 38h PCI Address Offset: 00000C0Ch Power-up value: Read/Write, Read/Write Clear PCI Attribute: 32 bits Size: Figure 29. Interrupt Control Status Register Actual ...
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S5920 – PCI Product: Operation Registers Table 41. Interrupt Control Status Register Bit 31:24 Reserved. Always zero. 23 Interrupt Asserted. This read only status bit indicates that one or more of the three possible interrupt conditions are present. This bit ...
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S5920 – PCI Product: Operation Registers PCI RESET CONTROL REGISTER (RCR) Reset Control Register Register Name: PCI Address 3Ch Offset: 00000000h Power-up value: Read/Write, Read Only, Write Attribute: Only 32 bits Size: Figure 30. FIFO Control/Status Register ...
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S5920 – PCI Product: Operation Registers Table 42. Reset Control Register Bit 31:29 nvRAM Access Control. This field provides a method for access to the optional external non-volatile memory. Write operations are achieved by a sequence of byte operations involving ...
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S5920 – PCI Product: Operation Registers PCI PASS-THRU CONFIGURATION REGIS- TER (PTCR) Pass-Thru Configuration Register Register Name: 60h PCI Address Offset: 80808080h Power-up value: Read/Write PCI Attribute: 32 bits Size: Figure 31. Pass-Thru Configuration Register Region 4 ...
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S5920 – PCI Product: Operation Registers Table 5 describes one of the four configuration registers. All four region configuration registers are exactly the same. Table 43. Bit 7 PTADR# mode. This bit is only valid in Active mode. If this ...
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S5920 – PCI Product: Operation Registers ADD-ON BUS OPERATION REGISTERS The Add-On bus interface provides access to 8 DWORDs of data, control and status information. All of these locations are accessed by asserting the Add-On bus chip select pin (SELECT#) ...
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S5920 – PCI Product: Operation Registers ADD-ON INCOMING MAILBOX REGISTER (AIMB) Incoming Mailbox Register Names: 0Ch Add-On Address: XXXXXXXXh Power-up value: Read Only Add-On Attribute: 32 bits Size: ADD-ON OUTGOING MAILBOX REGISTER (AOMB) Outgoing Mailbox Register Names: 1Ch Add-On Address: ...
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S5920 – PCI Product: Operation Registers ADD-ON MAILBOX EMPTY/FULL STATUS REGISTER (AMBEF) Mailbox Empty/Full Status Register Name: 34h Add-On Address: 00000000h Power-up value: Read Only Add-On Attribute: 32 bits Size: Figure 32. Mailbox Empty/Full Status Register Add-On ...
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S5920 – PCI Product: Operation Registers Table 45. Mailbox Empty/Full Status Register Bit 31:28 Add-On Outgoing Mailbox Status. This field indicates which byte of the outgoing mailbox register has been writ- ten by the Add-On interface but has not yet ...
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S5920 – PCI Product: Operation Registers ADD-ON INTERRUPT CONTROL/STATUS REGISTER (AINT) Add-On Interrupt Control and Status Register Name: 38h Add-On Address: 00000C0Ch Power-up value: Read/Write, Read/Write Clear Attribute: 32 bits Size: Figure 33. Add-On Interrupt Control Status Register Interrupt Status ...
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S5920 – PCI Product: Operation Registers Table 46. Interrupt Control Status Register Bit 31:24 Reserved. Always zero. 23 Interrupt Asserted. This read-only status bit indicates that one or more interrupt conditions are present. This bit is the OR of the ...
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S5920 – PCI Product: Operation Registers ADD-ON RESET CONTROL REGISTER (ARCR) Add-On Reset Control and Status Register Name: 3Ch Add-On Address: 00h Power-up value: Read/Write, Read Only, Write Only Attribute: 32 bits Size: Figure 34. Add-On General Control/Status Register 2 ...
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S5920 – PCI Product: Operation Registers Table 47. Reset General Control/Status Register Bit 31:29 nvRAM Access Control. This field provides a method for access to the optional external non-volatile memory. Write operations are achieved by a sequence of byte operations ...
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S5920 – PCI Product: Operation Registers ADD-ON PASS-THRU CONFIGURATION REGISTER (APTCR) Pass-Thru Configuration Register Register Name: 60h Add-On Address: 80808080h Power-up value: Read/Write Add-On Attribute: 32 bits Size: Figure 35. Pass-Thru Configuration Register Region 4 D7 Pass-Thru ...
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S5920 – PCI Product: Operation Registers The following describes one of the four configuration registers. All four region configuration registers are exactly the same. Table 48. Pass-thru Configuration Register Bit 7 PTADR# mode. This bit is only valid in Active ...
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S5920 – PCI Product: Initialization INTRODUCTION All PCI bus agents and bridges are required to imple- ment PCI Configuration Registers. When multiple PCI devices are present, these registers must be unique to each device in the system. The specified PCI ...
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S5920 – PCI Product: Initialization wire serial arbitration. It assumes that it is the only master on the bus. Communications with the serial memory involve sev- eral clock transitions. A start event signals the beginning of a transaction and is ...
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S5920 – PCI Product: Initialization Figure 36. S5920 to nvRAM Interface S5920 SCL SDA Figure 37. Serial Interface Definition of Start and Stop SCL SDA START BIT Figure 38. Serial Interface Clock Data Relationship SCL SDA DATA STABLE AMCC Confidential ...
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S5920 – PCI Product: Initialization Figure 39. Serial Interface Byte Access-Write S T SLAVE A ADDRESS R T 1010 Figure 40. Serial Interface Byte Access-Read S R/W T SLAVE A ADDRESS R T 1010 Figure 41. ...
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S5920 – PCI Product: Initialization NON-VOLATILE MEMORY INTERFACE The nv memory, can be accessed through the PCI interface or the Add-On interface. Accesses to the nv memory from the PCI interface are through the Reset Control Register (RCR). Accesses to ...
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S5920 – PCI Product: Initialization When performing a byte-wide RCR access, users need to write the command indicating how the data used, followed by the data. These commands will assert the internal signals LOAD_LOW_ADDR, LOAD_HIGH_ADDR or LOAD_WR_DATA. ...
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S5920 – PCI Product: Initialization could not use the busy bit to determine when to start a new write, but would need to insert a delay (deter- mined by the “shut down” time of the nvRAM, between 5-10 ms). Fortunately, ...
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S5920 – PCI Product: Initialization transfer was successful or not. If XFER_FAIL is asserted, this indicates that a transfer to the nvRAM did not receive an ACKNOWLEDGE. The read data in RCR(32:16) should not be consid- ered valid. This flag ...
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S5920 – PCI Product: Initialization Figure 44. Type 0 Configuration Write Cycles 0 12345 PCI CLK FRAME# AD[31:0] DATA ADD C/BE[3:0]# 1011 BYTE EN IRDY# TRDY# IDSEL DEVSEL# Table 50. PC Compatible Expansion ROM Byte Offset Byte Length (decimal) 0h ...
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S5920 – PCI Product: Initialization Table 50. PC Compatible Expansion ROM (Continued) Byte Offset Byte Length (decimal) 50h 1 51h 1 52h 1 53h 1 54h 4 58h 4 5Ch 4 60h 4 64h 4 68h 8 6Ch 2 6Eh ...
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S5920 – PCI Product: Initialization A 16-bit pointer at location 18h of the PC expansion ROM identifies the start offset of the PCI data struc- ture. The PCI data structure is shown in Table 3 and contains various vendor, product, ...
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S5920 – PCI Product: PCI Bus Protocol PCI BUS INTERFACE This section details various events which may occur on the S5920 PCI bus interface. Since the S5920 functions as a target or slave device, signal timing details are given for ...
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S5920 – PCI Product: PCI Bus Protocol Table 52. PCI Bus Commands (Continued) C/BE[3:0]# 1101 1110 1111 1. Memory Read Multiple and Memory Read Line are executed as a Memory Read. 2. Memory Write and Invalidate is executed as a ...
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S5920 – PCI Product: PCI Bus Protocol PCI READ TRANSFERS The S5920 responds to PCI bus memory or I/O read transfers when it is selected as a target. PCI targets may drive DEVSEL# and TRDY# after the end of the ...
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S5920 – PCI Product: PCI Bus Protocol Figure 47. Burst PCI Bus Write of S5920 Registers PCLK (I) FRAME# AD[31:0] Address Data 1 (I) Bus C/BE[3:0 Cmd (I) (I) IRDY# (T) TRDY# (T) DEVSEL# (T) ...
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S5920 – PCI Product: PCI Bus Protocol Target Latency The PCI specification requires that a selected target relinquish the bus should an access to that target require more than eight PCI clock periods (16 clocks for the first data phase, ...
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S5920 – PCI Product: PCI Bus Protocol Table 53. Target Termination Type Termination DEVSEL# STOP# Disconnect on on Retry on on Abort off on Targets selected with LOCK# deasserted during the assertion of FRAME# (clock period 1 of Figure 6), ...
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S5920 – PCI Product: PCI Bus Protocol PCI BUS INTERRUPTS The S5920 controller is able to generate PCI bus inter- rupts by asserting the PCI bus interrupt signal (INTA#). INTA multi-sourced, wire-ORed signal on the PCI bus and ...
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S5920 – PCI Product: PCI Bus Protocol Figure 52. Access to a Locked Target by its Owner PCLK (I) FRAME# LOCK# (I) AD[31:0] Address Data Data (I) IRDY RDY DEVSEL# LOCKED CONDIT ...
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S5920 – PCI Product: Mailbox Overview MAILBOX OVERVIEW The S5920 has two 32-bit mailbox registers. These mailboxes are useful for passing command and status information between the Add-On and the PCI bus. The PCI interface has one incoming mailbox (Add-On ...
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S5920 – PCI Product: Mailbox Overview Figure 56. Add-On to PCI Mailbox Register OUTPUT INTERLOCK REGISTER PCI BUS Q PCI CLK PCI READ Mailbox Empty/Full Conditions The PCI and Add-On interfaces each have a mailbox status register. The PCI Mailbox ...
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S5920 – PCI Product: Mailbox Overview PCI incoming mailbox interrupts, the S5920 asserts the PCI interrupt, INTA#. For Add-On incoming mail- box interrupts, the S5920 asserts the Add-On interrupt, IRQ#. For the outgoing mailbox interrupts, when the speci- fied byte ...
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S5920 – PCI Product: Mailbox Overview Add-On incoming and outgoing mailbox interrupts are enabled/disabled in the Add-On Interrupt Control/Sta- tus Register (AINT). The mailboxes can generate the Add-On IRQ# interrupt under two conditions (individu- ally enabled). For an incoming mailbox ...
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S5920 – PCI Product: Mailbox Overview Reading the PCI Incoming Mailbox: 1. Check Mailbox Status. Read the mailbox status register to determine if any information has been passed from the Add-On interface. MBEF Bits 31:28 2. Read Mailbox. Read the ...
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S5920 – PCI Product: Mailbox Overview Mailbox Interrupts Although polling status is useful in some cases, polling requires continuous actions by the processor. Mailbox inter- rupt capabilities are provided to avoid much of the processor overhead required by continuously polling ...
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S5920 – PCI Product: Mailbox Overview Servicing a PCI Mailbox Interrupt (INTA# asserted): 1. Identify the interrupt source(s). Multiple interrupt sources are available on the S5920. The interrupt service routine must verify that a mailbox generated the interrupt (and not ...
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S5920 – PCI Product: Mailbox Overview 4. Clear the interrupt source. The Add-On IRQ# signal is deasserted by clearing the interrupt request. The request is cleared by writing the appropriate bit. AINT Bit 17 AINT Bit 16 ...
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S5920 – PCI Product: Pass-Thru Operation ADD-ON LOCAL BUS INTERFACE This chapter describes the Add-On Local bus interface of the S5920. The S5920 is designed to support con- nection to a variety of microprocessor buses and/or peripheral devices. The Add-On ...
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S5920 – PCI Product: Pass-Thru Operation Figures 1 and 2 show basic operation register access timing relationships. Detailed AC timings are in Electri- cal and AC Characteristics. Chapter 10. For reads (Figure 1), data is driven onto the DQ bus ...
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S5920 – PCI Product: Pass-Thru Operation Figure 61. 16 Bit Mode Operation Register DWORD Write/Read 0 1234 ADCLK DQMODE SELECT# ADR[6:2] 60h BE3# BE[1:0]# 00b 10b WR# RD# DQ[15:0] 5678h Figure 3. 16 Bit Mode Operation Register DWORD Write/Read Figure ...
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S5920 – PCI Product: Pass-Thru Operation MAILBOX OVERVIEW For a detailed description of the Mailbox interface, ref- erence Chapter 8. PASS-THRU OVERVIEW The S5920 provides data transfers between the PCI bus and the user local bus through the Pass-Thru data ...
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S5920 – PCI Product: Pass-Thru Operation mation for the current PCI cycle. When the PCI bus performs burst accesses, the APTA register is incre- mented by the S5920 to reflect the address of the current data phase. PTNUM[1:0] is used ...
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S5920 – PCI Product: Pass-Thru Operation cycle decodes to one of the S5920 Pass-Thru regions, DEVSEL# is asserted. If the Pass-Thru logic is cur- rently idle (not busy finishing a previous Pass-Thru operation), the bus cycle type is decoded and ...
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S5920 – PCI Product: Pass-Thru Operation With many devices, particularly memories, the first access takes longer than subsequent accesses (assuming they are sequential and not random). For this reason, the PCI specification allows 16 clocks to respond to the first ...
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S5920 – PCI Product: Pass-Thru Operation S5920 PASSIVE MODE OPERATION The Pass-Thru address and data registers can be accessed as Add-On operation registers. The Pass- Thru FIFO is updated on the rising edge of ADCLK. For this reason, all Pass-Thru ...
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S5920 – PCI Product: Pass-Thru Operation Figure 62. PCI To Add-On Passive Write ADCLK PTATN# PTBURST# PTNUM[1:0] 1h PTWR PTBE[3:0] 0h SELECT# ADR[6:2] 2Ch BE[3:0]# 0h RD# DQ[31:0] PTRDY# Figure 63. PCI To Add-On Passive Write ...
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S5920 – PCI Product: Pass-Thru Operation address phase followed by a single data phase. If the S5920 determines that the address is within one of its defined Pass-Thru regions, it indicates to the Add-On a write to the Pass-Thru Data ...
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S5920 – PCI Product: Pass-Thru Operation Figure 65. PCI to Add-On Passive Burst Write ADCLK PTATN# PTBURST# PTNUM[1:0] PTWR PTBE[3:0] D1 SELECT# ADR[6:2] BE[3:0]# 0h RD# DQ[31:0] ADDR PTADR# PTRDY# Figure 7 shows a Passive mode PCI ...
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S5920 – PCI Product: Pass-Thru Operation Clock 3: The Add-On latches the address. Data 1 is driven on the DQ bus as a result of the previous read. As PTRDY# is sampled asserted, the PTBE# outputs are updated to indicate ...
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S5920 – PCI Product: Pass-Thru Operation Figure 66. PCI to Add-On Passive Burst Write Using PTRDY# to assert Wait-States ADCLK PTATN# PTBURST# PTNUM[1:0] PTWR PTBE[3:0] D1 SELECT# ADR[6:2] BE[3:0]# RD# DQ[31:0] PTADR# PTRDY# Figure 67. PCI to ...
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S5920 – PCI Product: Pass-Thru Operation Clock 1: Pass-Thru signals PTATN#, PTBURST#, PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi- cate what action is required by Add-On logic. These status signals are valid only when PTATN# is active. Add-On logic ...
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S5920 – PCI Product: Pass-Thru Operation address into the Pass-Thru Address Register (APTA). If the S5920 determines that the address is within one of its defined Pass-Thru regions, it indicates to the Figure 68. PCI to Add-On Passive Burst Read ...
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S5920 – PCI Product: Pass-Thru Operation DQ outputs to float before Add-On logic attempts to write to the Pass-Thru Read FIFO. Clock 4: The BE[3:0]#, ADR[6:2], and SELECT# inputs are asserted. WR# and DQ are asserted, indi- cating that DATA1 ...
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S5920 – PCI Product: Pass-Thru Operation will start servicing the Burst Read transfer by first read- ing the Pass-Thru Address via PTADR#. This is an asynchronous read, meaning that the address will appear on DQ after a propagation delay from ...
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S5920 – PCI Product: Pass-Thru Operation On operation registers, just the APTD register (ADR = 2Ch). Table 54. Byte Lane Steering for PCI Write (Add-On Read) Byte APTD Register Write Byte Lane Enables Steering DQ[31:24] DQ[23:16] ...
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S5920 – PCI Product: Pass-Thru Operation On bus signals PTATN#, PTBURST#, PTNUM[1:0], PTWR and PTBE[3:0] will update on the next ADCLK. Clock 1: Pass-Thru signals PTATN#, PTBURST#, PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi- cate what action is required ...
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S5920 – PCI Product: Pass-Thru Operation Clock 5: The Add-On logic latches BYTE1. RD# and BE2# are sampled asserted by the S5920, so BYTE2 of the APTD is driven on DQ[7:0] and PTBE2# is deas- serted. The Add-On device asserts ...
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S5920 – PCI Product: Pass-Thru Operation When the device is programmed for Big Endian trans- lation and a 32-bit data bus, the S5920 will convert as described in Table 3. Active mode is provided to simplify logic requirements when interfacing ...
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S5920 – PCI Product: Pass-Thru Operation Table 57. Big Endian conversion for a 16-bit bus. The S5920 drives D[15:0] only PCI Byte Transfer Byte # Lane 1st XFER 0 D7-D0 1st XFER 1 D15-D8 2nd XFER 2 D23-D16 2nd XFER ...
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S5920 – PCI Product: Pass-Thru Operation Figure 73. Active Mode PCI Write without PTADR ADCLK PTATN# PTBURST# PTNUM[1:0] 01b PTWR PTBE[3: DXFR# DQ[31:0] DATA PTWAIT# PTADR# When PTADR# is active (low), the S5920 will ...
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S5920 – PCI Product: Pass-Thru Operation Figure 75. Active Mode 32-Bit PCI Write ADCLK PTATN# PTBURST# 01b PTNUM[1:0] PTWR 0h PTBE[3:0] DXFR# DATA DQ[31:0] PTADDR PTWAIT# PTADR# The address phase of a Pass-Thru consists of the cycles ...
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S5920 – PCI Product: Pass-Thru Operation Figure 76. Active Mode 32-Bit PCI Write w/PTWAIT ADCLK PTATN# PTBURST# PTNUM[1:0] PTWR Data1 Data2 PTBE[3:0]# DXFR# DATA1 DQ[31:0] PTADR# PTWAIT# Clock by Clock description of Figure 16 Clock 1: The ...
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S5920 – PCI Product: Pass-Thru Operation Clock 9: DXFR# is sampled active (low) by the Add- On device which indicates that the Add-On device must latch the fourth data word at the rising edge of this clock. PTATN# is driven ...
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S5920 – PCI Product: Pass-Thru Operation Clock 2: Since this region does have PTADR# enabled as an output driven active (low) and the PCI address for the current transaction is presented on the DQ[31:0] bus. Clock 3: The ...
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S5920 – PCI Product: Pass-Thru Operation Figure 80. Active Mode PCI Read ADCLK PTATN# PTBURST# 1h PTNUM[1:0] PTWR PTBE[3: DXFR# LOW HIGH DQ[15:0] PTWAIT# PTADR# Figure 20 shows a Pass-Thru write cycle with 0 wait ...
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S5920 – PCI Product: Pass-Thru Operation S5920 Base Address Register Definition Certain bits in the Base Address Register have spe- cific functions: Memory or I/O mapping. If this bit is clear, the D0 region should be memory mapped. If this ...
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S5920 – PCI Product: Pass-Thru Operation After the host reads all Base Address Registers in the system (as every PCI device implements from one to six), the PCI BIOS allocates memory and I/O space to each Base Address region. The ...
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S5920 – PCI Product: Pass-Thru Operation (disconnect, but with no data transfer), the read data is held in the FIFO until the master comes back for it. In this case, the Retry Flush Enb has no effect. The PCI 2.1 ...
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S5920 – PCI Product: Electrical Characteristics ABSOLUTE MAXIMUM STRESS RATINGS Table 1 lists the absolute maximum S5920 device stress ratings. Stresses beyond those listed may cause perma- nent damage to the device. These are stress ratings only; operation of the ...
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S5920 – PCI Product: Electrical Characteristics PCI Signal DC Characteristics The following table summarizes the DC characteristic parameters for all PCI signals listed below as they apply to the S5920. AD[31:0] (t/s), PAR (t/s), C/BE[3:0]# (in), FRAME# (in), IRDY# (in), ...
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S5920 – PCI Product: Electrical Characteristics Add-On Signal DC Characteristics The following table summarizes the Add-On DC characteristic parameters for the Add-On signals listed below as they apply to the S5920. All Add-On signal outputs listed are capable of sinking ...
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S5920 – PCI Product: Electrical Characteristics TIMING SPECIFICATION PCI Clock Specification Table 5 summarizes the A. C. characteristics for the PCI bus signals as they apply to the S5920. The figures after Table 5 visually indicate the timing relationships. Table ...
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S5920 – PCI Product: Electrical Characteristics Figures 2 and 3 define the conditions under which timing measurements are made. The user designs must guaran- tee that minimum timings are met with maximum clock skew rate (fastest edge) and voltage swing. ...
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S5920 – PCI Product: Electrical Characteristics Table 6 summarizes the A. C. characteristics for the Add-On bus signals as they apply to the S5920. The figures after Table 6 visually indicate the timing relationships. Table 64. Add-On Timings, Functional Operation ...
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S5920 – PCI Product: Electrical Characteristics Table 64. Add-On Timings, Functional Operation Range (V = 5.0 V ± 5%, 0° 0° load on outputs for MAX load for MIN) (Continued) CC Symbol Parameter t ...
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S5920 – PCI Product: Electrical Characteristics Figure 86. Add-On Clock Timing 2.0 0.8 Figure 87. Pass-Thru Clock Relationship to PCI Clock PCI CLK BPCLK Figure 88. PTADR Timing PTADR# DQ[31:0] AMCC Confidential and Proprietary t 10 2.0 V IH2 0.8 ...
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S5920 – PCI Product: Electrical Characteristics Figure 89. Passive Mode Pass-Thru Operation ADCLK PTATN PTBURST PTNUM[1: PTWR t 24 PTBE[3: PTRDY# SELECT# ADR[6:2] BE[3:0] RD# DQ[31:0] WR# DQ[31:0] AMCC Confidential and Proprietary ...
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S5920 – PCI Product: Electrical Characteristics Table 65. Add-On Timings Functional Operation Range (V CC Symbol t DXFER# Valid from ADCLK Rising Edge 45 t DXFER# Hold from ADCLK Rising Edge 46 t PTADR# Valid from ADCLK Rising Edge 47 ...
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S5920 – PCI Product: Electrical Characteristics Figure 90. Active Mode Pass-Thru Write Operation ADCLK PTATN PTBURST# PTNUM[1: PTWR t 24 PTBE[3: DXFER# PTWAIT# PTADR# DQ[31:0] AMCC Confidential and Proprietary Revision 1.02 – April 12, ...
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S5920 – PCI Product: Electrical Characteristics Table 66. Mailbox Timings Functional Operation Range (V CC Symbol t LOAD# Setup to ADCLK Rising Edge 60 t LOAD# Hold from ADCLK Rising Edge 61 t MD[7:0] Setup to ADCLK Rising Edge 62 ...
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S5920 – PCI Product: Electrical Characteristics Figure 93. S5920 Pinout and Pin Assignment GND 121 PTNUM1 122 PTNUM0 123 IRQ# 124 DQ19 125 SYSRST# 126 SDA 127 SCL 128 VCC 129 GND 130 VCC 131 ADR6 132 DQ18 133 ADCLK ...
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S5920 – PCI Product: Electrical Characteristics Figure 94. 160 PQFP ( 3.37 mm) - Plastic Quad Flat Package AMCC Confidential and Proprietary Revision 1.02 – April 12, 2007 Data Book DS1596 162 ...
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S5920 – PCI Product: Electrical Characteristics S5920 – 160 PQFP PACKAGE MARKING DRAWING Figure 95. S5920 – 160 PQFP Package Marking Drawing (Top View) NOTES (Unless Otherwise Specified): Dot Represents PIN 1 (A01) Designator 1 ES (Engineering Sample) designator. When ...
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S5920 – PCI Product: Electrical Characteristics DOCUMENT REVISION HISTORY Revision Date 1.02 04/12/07 • Page 163, Added Marking Drawing • Page 165, Updated ordering information format 1.01 09/21/05 • Updated ordering information AMCC Confidential and Proprietary Revision 1.02 – April ...
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... S5920 – PCI Product: Electrical Characteristics ORDERING INFORMATION Device Code S5920Q S5920 - PCI Product Standard Package, Commercial Temp S5920QRC S5920 - PCI Product Green/RoHS Compliant Package, Commercial Temp S5920 X Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 AMCC reserves the right to make changes to its products, its data sheets, or related documentation without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available data sheet. Please consult AMCC’ ...