S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 4

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product
CACHE LINE SIZE REGISTER (CALN) ............................................................................................................... 54
LATENCY TIMER REGISTER (LAT) .................................................................................................................... 55
HEADER TYPE REGISTER (HDR) ....................................................................................................................... 56
BUILT-IN SELF-TEST REGISTER (BIST) ............................................................................................................ 57
BASE ADDRESS REGISTER (BADR) ................................................................................................................. 58
SUBSYSTEM VENDOR IDENTIFICATION REGISTER (SVID) ........................................................................... 63
SUBSYSTEM ID REGISTER (SID) ....................................................................................................................... 64
EXPANSION ROM BASE ADDRESS REGISTER (XROM) ................................................................................. 65
INTERRUPT LINE REGISTER (INTLN) ................................................................................................................ 67
INTERRUPT PIN REGISTER (INTPIN) ................................................................................................................ 68
MINIMUM GRANT REGISTER (MINGNT) ............................................................................................................ 69
MAXIMUM LATENCY REGISTER (MAXLAT) ...................................................................................................... 70
OPERATION REGISTERS .................................................................................................................................... 71
PCI BUS OPERATION REGISTERS .................................................................................................................... 71
OUTGOING MAILBOX REGISTER (OMB) ........................................................................................................... 72
PCI INCOMING MAILBOX REGISTER (IMB) ....................................................................................................... 73
PCI MAILBOX EMPTY/FULL STATUS REGISTER (MBEF) ................................................................................ 74
PCI INTERRUPT CONTROL/STATUS REGISTER (INTCSR) ............................................................................. 75
PCI RESET CONTROL REGISTER (RCR) ........................................................................................................... 77
AMCC Confidential and Proprietary
Base Class Code 0Bh: Processors ................................................................................................................. 53
Base Class Code 0Ch: Serial Bus Controllers ................................................................................................ 53
Cache Line Size Register ................................................................................................................................ 54
Latency Timer Register ................................................................................................................................... 55
Header Type Register ..................................................................................................................................... 56
Built-In Self-Test Register ................................................................................................................................ 57
Determining Base Address Size ...................................................................................................................... 58
Assigning the Base Address ............................................................................................................................ 58
Base Address Register - Memory .................................................................................................................... 59
Base Address Register - I/O ............................................................................................................................ 60
Base Address Register Response (Memory Assigned) to All-Ones Write Operation ..................................... 61
Read Response (I/O Assigned) to an All-Ones Write Operation to a Base Address Register ........................ 62
Subsystem Vendor Identification Register ....................................................................................................... 63
Subsystem Identification Register ................................................................................................................... 64
Expansion ROM Base Address Register ......................................................................................................... 65
Read Response to Expansion ROM Base Address Register (after all ones written) ...................................... 66
Interrupt Line Register ..................................................................................................................................... 67
Interrupt Pin Register ....................................................................................................................................... 68
Minimum Grant Register .................................................................................................................................. 69
Maximum Latency Register ............................................................................................................................. 70
Operation Registers - PCI Bus ........................................................................................................................ 71
Outgoing Mailbox ............................................................................................................................................. 72
Incoming Mailbox ............................................................................................................................................. 73
Mailbox Empty/Full Status Register (MBEF) ................................................................................................... 74
Mailbox Empty/Full Status Register ................................................................................................................. 74
Interrupt Control Status Register ..................................................................................................................... 75
Interrupt Control Status Register ..................................................................................................................... 76
Revision 1.02 – April 12, 2007
Data Book
DS1596
4