Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 74

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Master Interrupt Enable
Interrupt Vectors and Priority
System Exceptions
The master interrupt enable bit in the flag register globally enables or disables interrupts.
This bit has been moved to the flag register (bit 0). Thus, anytime the register is loaded, it
changes the state of the IRQE bit. For the
been pushed on the stack.
Interrupts are globally enabled by any of the following actions:
•
•
Interrupts are globally disabled by any of the following actions:
•
•
•
•
•
•
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all the
interrupts are enabled with identical interrupt priority (for example, all interrupts enabled
as Level 2 interrupts), the interrupt priority is assigned from highest to lowest as specified
in
rupts, which in turn, always have higher priority than Level 1 interrupts. Within each inter-
rupt priority levels (Level 1, Level 2, or Level 3), priority is assigned as specified in
Table 27. Reset and System Exceptions have the highest priority.
System Exceptions are generated for stack overflow, illegal instructions, divide-by-zero,
and divide overflow, etc. The System Exceptions are not affected by the IRQE and share a
single vector.
Each exception has a bit in the system exception status register. When a system exception
occurs it pushes the program counter and the flags on the stack, fetches the system excep-
tion vector from
set in the status register. Additional exceptions from the same source are blocked until the
status bit of the particular exception is cleared by writing 1 to that status bit. Other types of
Table 27
Execution of an Enable Interrupt (
Writing 1 to the IRQE bit in the flag register
Execution of a Disable Interrupt (
CPU acknowledgement of an interrupt service request from the interrupt controller
Writing 0 to the IRQE bit in the flag register
Reset
Execution of a
All System Exceptions
on page 49. Level 3 interrupts always have higher priority than Level 2 inter-
000008H
TRAP
instruction
P R E L I M I N A R Y
(similar to a IRQ) and the bit associated with that exception is
DI
EI
) instruction
) instruction
IRET
Z16FMC Series Motor Control MCUs
instruction the bit is set based on what has
Product Specification
Interrupt Controller
52