Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 182

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
ESPI Baud Rate Generator
master, the valid options are transmit only or transmit-receive. For a slave, all options are
valid. When a slave is operating in receive only mode, it will transmit characters of all 1s.
DMA Descriptors
For ESPI Transmit DMA descriptors, the 4-bit
the format shown in Table 86. The SSV bit in the Master’s transmit buffer descriptor
STAT
SSV bit in the ESPI Data Command register with the first byte of the buffer. If the EOF bit
is set in the DMA descriptor control word, the End Of Frame signal from the DMA (EOF-
Sync) will assert coincident with writing the final byte in the buffer to the ESPI Data Reg-
ister, setting the TEOF bit of the ESPI Data Command register. After this final byte has
been transferred, the Master’s SS output will deassert and the SSV and TEOF bits in the
Data Command register will be cleared. The
Descriptors has no function.
Table 86. ESPI Tx DMA Descriptor Command Field
For ESPI DMA descriptors, the 4-bit frame status field of the descriptor is depicted in the
formats shown in Tables 87 and 88.
Table 87. ESPI Tx DMA Descriptor Status field
Table 88. ESPI Rx DMA Descriptor Status field
TUND, COL, ABT, ROVR.
RSS.
right channel data).
In ESPI MASTER mode, the BRG creates a lower frequency serial clock (SCK) for data
transmission synchronization between the Master and the external Slave. The input to the
BRG is the system clock. The ESPI Baud Rate High and Low Byte registers combine to
form a 16-bit reload value, BRG[15:0], for the ESPI BRG. The ESPI baud rate is calcu-
lated using the following equation:
Reserved
Value of SS associated with final byte written (useful in I2S mode to distinguish left/
field controls the ESPI SS output. The SSV bit in the descriptor is transferred to the
0
0
Reserved
RSS
0
P R E L I M I N A R Y
See the Status Register for a description of these bits.
Reserved
COL
ABT
ROVR
TUND
CMDSTAT
SSV
CMDSTAT
Z16FMC Series Motor Control MCUs
Enhanced Serial Peripheral Interface
field in ESPI Receive DMA
field of the descriptor exists in
Product Specification
CMD-
160