Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 253

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
DMA Interrupts
Each DMA has equal priority under this scheme.
DMA Bandwidth Selection
In the CPUCTL register, the DMABW mode bits set the maximum bus bandwidth the
DMA is allowed; there are four modes. (For more detail, refer to the
Manual
Table 122 lists the DMA bandwidth selection.
Table 122. DMA Bandwidth Selection
Each DMA has its own interrupt vector. For additional information about the interrupts,
see the
Interrupts occur on the following conditions:
•
•
•
Bits
00
01
10
11
Whenever a buffer is completed which has its IEOB set
When the upper eight bits of the transfer length equal zero and the lower eight bits of
the transfer length is equal to the DMAxLAR[23:16] and the DMA is in direct mode
If a buffer has been terminated by a Request EOF
Interrupt Controller
(UM0188), which is available for download from the Zilog website.)
Description
DMA uses 100% of the bandwidth
DMA is allowed one transfer for each CPU operation
DMA is allowed one transfer for every two CPU operations
DMA is allowed one transfer for every three CPU operations
P R E L I M I N A R Y
chapter on page 49.
Z16FMC Series Motor Control MCUs
Product Specification
ZNEO CPU User
DMA Controller
231