Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 235

Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D

Z16FMC32AG20EG

Manufacturer Part Number
Z16FMC32AG20EG
Description
Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet

Specifications of Z16FMC32AG20EG

Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
- 40 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z16FMC32AG20EG
Manufacturer:
Zilog
Quantity:
160
Part Number:
Z16FMC32AG20EG
Manufacturer:
Zilog
Quantity:
10 000
Table 116. ADC0 MAX Register (ADC0MAX)
Table 117. ADC Timer0 Capture Register, high byte (ADCTCAP_H)
PS028702-1210
Bit Position
[0]
DIV2
Bit Position
[7:4]
[3:0]
LASTCHAN0
Bits
Field
RESET
R/W
ADDR
Bits
Field
RESET
R/W
ADDR
ADC0 Max Register
ADC Timer0 Capture Register
7
7
The ADC0 Max register. This register determines the highest channel that the Convert on
Read increments too.
The ADC Timer0 Capture register contains the sixteen bits of the ADC Timer0 count and
can read a 16-bit word or read 8 bits at a time. Access to the ADC Timer0 Capture register
is read-only.
Value (H) Description (Continued)
Value (H) Description
0H
0
1
0
Reserved; must be 0.
LAST CHANNEL0
These bits determine the final channel number to increment to when the Con-
vert On Read is set.
6
6
DIV2
Clock is not divided.
System Clock is divided by 2 for ADC Clock.
Reserved
0
5
5
P R E L I M I N A R Y
4
4
ADCTCAPH
FF_E507H
FF_E512H
R/W
R
X
Z16FMC Series Motor Control MCUs
3
3
LASTCHAN0
2
2
Product Specification
0H
1
1
Analog Functions
0
0
213

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