Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 293

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Serial Errors
Interrupts
DBG pin used as a GPIO pin
vents data written to the Transmit Data Register from being transmitted on the single pin
interface.
If the UART is disabled, data is still written to the Receive Data Register and read from
the Transmit Data Register. These actions still generates UART interrupts. The UARTEN
control bit only prevents data from being transmitted to or received from the DBG pin.
The serial interface detects the following error conditions:
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Transmission of data is prevented if the transmit collision, receive framing error, receive
break detect, receive overrun, or receive data register full status bits are set.
The Debug UART generates interrupts during the following conditions:
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The DBG pin is used as a GPIO pin. The serial interface cannot be used for debugging
when the DBG pin is configured as a GPIO pin. To set up the DBG pin as a GPIO pin,
software must clear the
Software uses the pin as an input by clearing the output enable control bit. The PIN status
bit in the Line Control Register (DBGLCR) reflects the state of the DBG pin.
The DBG pin is configured as an output pin by setting the output enable control bit. The
logic state of the IDLE bit in the Line Control Register (DBGLCR) is driven onto the
DBG pin.
Receive framing error (received Stop bit is Low)
Transmit collision (OCD releases the bus high to send a logic 1 and detects it is Low)
Receive overrun (received data before previously received data read)
Receive break detect (10 or more bits Low)
Receive Data Register is Full (includes Rx Framing Error and Rx Overrun Error)
Transmit Data Register is empty
Auto-Baud Detector loads the BRG (auto-baud character received)
Receive Break detected
DBGUART
P R E L I M I N A R Y
option bit and
Z16FMC Series Motor Control MCUs
OCDEN
control bit.
Product Specification
On-Chip Debugger
271