Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 299

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

Table 159. OCD Control Register (OCDCTL)
PS028702-1210
Bits
3
2
1
0
Bits
Field
RESET
R/W
Bits
7
OCD Control Register
Description (Continued)
CRCEN – CRC enable
If this bit is set, a CRC is appended to the end of each debug command. Clearing this bit will
disable transmission of the CRC.
0 = CRC disabled
1 = CRC enabled
UARTEN – UART enable
This bit is used to enable or disable the UART. This bit is ignored when OCDEN is set.
0 = UART Disabled.
1 = UART Enabled.
ABCHAR – Auto-baud character
This bit selects the character used during auto-baud detection. This bit cannot be written by the
CPU if OCDEN is set.
0 = Auto-baud character to be measured is 80H.
1 = Auto-baud character to be measured is 0DH.
ABSRCH – Auto-baud search mode
This bit enables auto-baud search mode. When this bit is set, the next character received is
measured to set the Baud Rate Reload register. This bit clears itself to zero after the reload
register has been written. This bit is automatically set when OCDEN is set if a serial communica-
tion error occurs. This bit cannot be written by the CPU if the OCDEN bit is set.
0 = Auto-baud search disabled.
1 = Auto-baud search enabled.
Description
DBGHALT – Debug halt
Setting this bit to one causes the device to enter Debug Halt mode. When in Debug Halt mode,
the CPU stops fetching instructions. Clearing this bit causes the CPU to start running again.
This bit is automatically set to 1 when a breakpoint occurs if the BRKHALT bit is set.
0 = The device is running.
1 = The device is in Debug Halt mode.
DBGHALT BRKHALT
R/W
7
0
The OCD Control Register (OCDCTL) controls the state of the CPU. This register puts
the CPU in Debug Halt Mode, enable breakpoints, or single step an instruction.
R/W
6
0
BRKEN
R/W
5
0
P R E L I M I N A R Y
STOP
DBG-
R/W
4
0
Z16FMC Series Motor Control MCUs
3
Reserved
000
R
2
Product Specification
On-Chip Debugger
1
STEP
R/W
0
0
277