Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 169

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

ESPI Signals
PS028702-1210
Master-In/Slave-Out
Master-Out/Slave-In
Serial Clock
The four ESPI signals are:
•
•
•
•
The following paragraphs describe these signals in both MASTER and SLAVE modes.
The appropriate GPIO pins must be configured using the GPIO alternate function regis-
ters.
The MISO pin is configured as an input in a master device and as an output in a slave
device. Data is transferred to most significant bit first. The MISO pin of a slave device is
placed in a high-impedance state if the slave is not selected. When the ESPI is not enabled,
this signal is in a high-impedance state. The direction of this pin is controlled by the
bit of the ESPI control register.
The MOSI pin is configured as an output in a master device and as an input in a slave
device. Data is transferred to most significant bit first. When the ESPI is not enabled, this
signal is in a high-impedance state. The direction of this pin is controlled by the
of the ESPI control register.
The SCK synchronizes data movement both in and out of the shift register via the MOSI
and MISO pins. In MASTER mode (
serial clock and drives it out via its SCK pin to the slave devices. In SLAVE mode, the
SCK pin is an input. Slave devices ignore the SCK signal unless their SS pin is asserted.
The master and slave are each capable of exchanging a character of data during a sequence
of NUMBITS clock cycles (see NUMBITS field in the the
page 165). In both master and slave ESPI devices, data is shifted on one edge of the SCK
and is sampled on the opposite edge where data is stable. SCK phase and polarity is deter-
mined by the
163.
Master-In/Slave-Out (MISO)
Master-Out/Slave-In (MOSI)
Serial clock (SCK)
Slave select (SS) 
Phase
and
CLKPOL
P R E L I M I N A R Y
bits in the the
MMEN = 1
), the ESPI’s baud rate generator creates the
Z16FMC Series Motor Control MCUs
ESPI Control Register
Enhanced Serial Peripheral Interface
ESPI Mode Register
Product Specification
section on page
section on
MMEN
MMEN
bit
147