Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 112

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Synchronization of PWM and ADC
Synchronized Current-Sense Sample and Hold
PWM Timer and Fault Interrupts
Fault Detection and Protection
where
The ADC on the Z16FMC is synchronized with the PWM period. Enabling the PWM
ADC trigger causes the PWM to generate an ADC conversion signal at the end of each
PWM period. Additionally, in CENTER-ALINGED mode, the PWM generates a trigger at
the center of the period. Setting the ADCTRIG bit in the PWM Control 0 Register
(PWMCTL0) enables the ADC synchronization.
The PWM controls the current-sense input sample and hold amplifier. The signal control-
ling the sample/hold is configured to always sample or automatically hold when any or all
the PWM High or Low outputs are in the on state. The current-sense sample and hold is
controlled by the Current-Sense Sample and Hold Control Register (CSSHR0 and
CSSHR1).
The PWM generates interrupts to the CPU during any of the following events:
PWM Reload.
ter reload occurs.
PWM Fault.
tion of the comparator.
The Z16FMC contains hardware and software fault controls, which allow rapid deasser-
tion of all enabled PWM output signals. A logic Low on an external fault pin (FAULT0 or
FAULT1) or the assertion of the over current comparator forces the PWM outputs to the
predefined off-state.
Similar deassertion of the PWM outputs is accomplished in software by writing to the
PWMOFF bit in the PWM Control 0 Register. The PWM counter continues to operate
while the outputs are deasserted (inactive) due to one of these fault conditions.
The fault inputs are individually enabled through the PWM fault control register. If a fault
condition is detected and the source is enabled, the fault interrupt is generated. The PWM
Fault Status Register (PWMFSTAT) is read to determine which fault source caused the
interrupt.
T
roundup PWMMPF
minPulseOut
A fault condition is indicated by asserting any FAULT pins or by the asser-
The interrupt is generated at the end of a PWM period when a PWM regis-

is the shortest allowed pulse width on the PWM outputs (in seconds).

P R E L I M I N A R Y
=
T
minPulseOut


T
systemClock
Z16FMC Series Motor Control MCUs

PWMprescaler
Multi-Channel PWM Timer
Product Specification

90