Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 233

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

Table 113. Sample and Settling Time (ADCSST)
PS028702-1210
Bit Position
[7:5]
[4:0]
SST
Bits
Field
RESET
R/W
ADDR
Bit Position Value (H) Description
[7:6]
[5:0]
Reserved
Sample Settling Time Register
Sample Time Register
00H –1FH
Value (H) Description
7
0
The sample settling time register is used to program the length of time from the SAMPLE/
HOLD signal to the START signal, when the conversion begins. The number of clock
cycles required for settling varies from system to system depending on the system clock
period used. You must program this register to contain the number of clocks required to
meet a 0.5 S minimum settling time.
The sample time register is used to program the length of active time for the sample after a
conversion has begun by setting the
the PWM. The number of system clock cycles required for sample time varies from sys-
tem to system depending on the clock period used. You must program this register to con-
tain the number of system clocks required to meet a 1 s minimum sample time.
00–11b
0H
0
Reserved
ADC0 Low Bits
These bits are the 2 least significant bits of the 10-bit ADC0 output. These bits
are undefined after a Reset.
Reserved – Must Be 0.
Reserved – must be 0.
Sample Settling Time
Sample settling time in number of system clock periods to meet 0.5 s mini-
mum.
R
6
0
5
0
P R E L I M I N A R Y
4
1
START
FF_E504H
bit in the ADC control register or initiated by
Z16FMC Series Motor Control MCUs
3
1
SST
R/W
2
1
Product Specification
1
1
Analog Functions
0
1
211