Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 209

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

s
PS028702-1210
S
Slave Address
Figure 39. Data Transfer Format – Slave Receive Transaction with 10-Bit Address
1st Byte
2. The bus Master initiates a transfer, sending the address byte. The Slave mode I
3. Software responds to the interrupt by reading the I2CISTAT Register (which clears the
4. The Master detects the acknowledge and sends the byte of data.
5. The I
6. Software responds by reading the I2CISTAT Register, finding the
7. The Master and Slave loop on steps 4–6 until the Master detects a Not Acknowledge
8. The Master sends the STOP or RESTART signal on the bus. Either of these signals
Slave Receive Transaction with 10-Bit Address
The data transfer format for writing data from Master to Slave with 10-bit addressing is
shown in Figure 39. The following procedure describes the I
operating as a Slave in 10-bit addressing mode, receiving data from the bus Master.
1. Software configures the controller for operation as a Slave in 10-bit addressing mode
e. Program the Baud Rate High and Low Byte registers for the I
Controller recognizes its own address and detects the R/W bit = 0 (write from Master
to Slave). The I
transaction.The
RD
Controller holds the SCL signal Low, waiting for software to load the first data byte.
SAM
0, no immediate action is required until the first byte of data is received. If software is
only able to accept a single byte it sets the
Acknowledge depending on the state of the
controller generates the receive data interrupt by setting the
Register.
reading the I2CDATA Register clearing the
more data byte, it sets the
instruction or runs out of data to send.
cause the I
Register). When the Slave receive data from the Master, software takes no action in
response to the Stop interrupt other than reading the I2CISTAT Register, clearing the
STOP bit in the I2CISTAT Register.
as follows.
bit in the I2CISTAT Register is set = 0, indicating a write to the Slave. The I
bit). After verifying that the
2
W=0
C controller receives the data byte and responds with Acknowledge or Not
2
C Controller to assert the Stop interrupt (STOP bit = 1 in the I2CISTAT
A
2
SAM
C Controller acknowledges, indicating it is available to accept the
Slave Address
bit in the I2CISTAT Register is set = 1, causing an interrupt. The
2nd Byte
P R E L I M I N A R Y
NAK
bit in the I2CCTL Register.
SAM
A
bit = 1, software checks the
NAK
Data
Z16FMC Series Motor Control MCUs
NAK
RDRF
bit in the I2CCTL Register at this time.
bit in the I2CCTL Register. The I
bit. If software accepts only one
A
2
C Master/Slave Controller
I2C Master/Slave Controller
RDRF
Product Specification
Data
2
bit in the I2CISTAT
RD
RDRF
C baud rate.
bit. When
bit=1 and
A/A
2
2
C
RD
P/S
C
2
C
=
187