Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 15

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Figure 31. ESPI Configured as an SPI Master in a Single Master and Multiple Slave
Figure 32. ESPI Configured as an SPI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 33. I2C Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 34. Data Transfer Format – Master Write Transaction with a 7-Bit Address . 179
Figure 35. Data Transfer Format – Master Write Transaction with 10-Bit Address . 180
Figure 36. Data Transfer Format – Master Read Transaction with 7-Bit Address . . . 182
Figure 37. Data Transfer Format – Master Read Transaction with 10-Bit Address . . 183
Figure 38. Data Transfer Format – Slave Receive Transaction with 7-Bit Address . . 186
Figure 39. Data Transfer Format – Slave Receive Transaction with 10-Bit Address . 187
Figure 40. Data Transfer Format – Slave Transmit Transaction with 7-bit Address . 189
Figure 41. Data Transfer Format – Slave Transmit Transaction with 10-Bit Address 190
Figure 42. Analog Functions Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 43. ADC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 44. ADC Convert Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 45. DMA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 46. DMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 47. Direct DMA Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 48. Linked List Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 49. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Figure 50. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 51. Interfacing the serial pin with an RS-232 Interface (1) . . . . . . . . . . . . . . . 256
Figure 52. Interfacing the serial pin with an RS-232 Interface (2) . . . . . . . . . . . . . . . 257
Figure 53. OCD Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Figure 54. Output Driver when Drive High and Open Drain enabled . . . . . . . . . . . . 260
Figure 55. 9-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 56. Start Bit Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 57. Initialization during Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 58. Recommended 20 MHz Crystal Oscillator Configuration . . . . . . . . . . . . 283
Figure 59. Connecting the On-Chip Oscillator to an External RC Network . . . . . . . . 284
Figure 60. Typical RC Oscillator Frequency as a Function of the External Capacitance
Figure 61. Typical Idd Versus System Clock Frequency . . . . . . . . . . . . . . . . . . . . . . 295
Figure 62. Typical HALT Mode Idd Versus System Clock Frequency . . . . . . . . . . . 296
Figure 63. Stop Mode Current Versus Vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Figure 64. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
with a 15 k
Ω
Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
P R E L I M I N A R Y
Z16FMC Series Motor Control MCUs
Product Specification
List of Figures
xv