Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 208

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
S
Slave Address
Figure 38. Data Transfer Format – Slave Receive Transaction with 7-Bit Address
received data byte before deciding to set or clear the
acknowledged (requirement the I
Software address recognition.
must be set = 1 prior to the reception of the address byte(s). When
byte generates a receive interrupt (
examine each byte and determine whether to set or clear the
Low during the acknowledge phase until software responds by writing to the I2CCTL
Register. The value written to the
then releasing the SCL. The
phase, but the
Slave Transaction Diagrams
In the following transaction diagrams, shaded regions indicate data transferred from the
Master to the Slave and unshaded regions indicate data transferred from the Slave to the
Master. The transaction field labels are defined as follows:
Slave Receive Transaction with 7-Bit Address
The data transfer format for writing data from Master to Slave in 7-bit address mode is
shown in Figure 38. The following procedure describes the I
operating as a Slave in 7-bit addressing mode, receiving data from the bus Master.
1. Software configures the controller for operation as a Slave in 7-bit addressing mode as
S
W
A
A
P
follows.
a. Initialize the MODE field in the I
b. Optionally set the
c. Initialize the
d. Set
Start
Write
Acknowledge
Not Acknowledge
Stop
mode or Master/Slave mode with 7-bit addressing.
IEN
W=0
RD
= 1 in the I
bit is updated based on the first address byte.
A
SLA
[6:0] bits in the I
GCE
P R E L I M I N A R Y
2
SAM
C Control Register. Set
Data
bit.
2
To disable the hardware address recognition, the
and
NAK
C specification).
RDRF
GCA
bit is used by the controller to drive the I
A
= 1 in the I2CISTAT Register). Software must
2
bits are not set when
2
C Mode Register for either SLAVE-ONLY
C Slave Address Register.
Z16FMC Series Motor Control MCUs
Data
NAK
NAK
= 0 in the I
bit. A START byte will not be
A
NAK
2
C Master/Slave Controller
I2C Master/Slave Controller
IRM
Product Specification
bit. The Slave holds SCL
Data
IRM
= 1 during the address
2
C Control Register.
= 1 each received
A/A
2
C Bus,
IRM
P/S
bit
186