Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 223

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

Table 106. I2CSTATE_H
PS028702-1210
Bits
7:4
3:0
State Encoding
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
Description
I2CSTATE_H – I
This field defines the current state of the I
internal state machine. Table 106 defines the states for this field.
I2CSTATE_L – Least significant nibble of the I
This field defines the substates for the states defined by I2CSTATE_H. Table 107 defines the
values for this field.
State Name
Idle
Slave Start
Slave Bystander
Slave Wait
Master Stop2
Master Start/Restart
Master Stop1
Master Wait
Slave Transmit Data
Slave Receive Data
Slave Receive Addr1
Slave Receive Addr2
Master Transmit Data
Master Receive Data
2
C State
P R E L I M I N A R Y
State Description
I
I
Address did not match – ignore remainder of transaction.
Waiting for STOP or RESTART condition after sending a Not
Acknowledge instruction.
Master completing STOP condition (SCL = 1, SDA = 1).
Master mode sending START condition (SCL = 1, SDA = 0).
Master initiating STOP condition (SCL = 1, SDA = 0).
Master received a Not Acknowledge instruction, waiting for
software to assert STOP or START control bits.
Nine substates, one for each data bit and one for the acknowl-
edge.
Nine substates, one for each data bit and one for the acknowl-
edge.
Slave Receiving first address byte (7 and 10 bit addressing)
Nine substates, one for each address bit and one for the
acknowledge.
Slave Receiving second address byte (10 bit addressing)
Nine substates, one for each address bit and one for the
acknowledge.
Nine substates, one for each data bit and one for the acknowl-
edge.
Nine substates, one for each data bit and one for the acknowl-
edge.
2
2
C bus is idle or I
C Controller has received a start condition.
2
C Controller. It is the most significant nibble of the
2
C state machine.
2
C Controller is disabled.
Z16FMC Series Motor Control MCUs
I2C Master/Slave Controller
Product Specification
201