Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 189

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

Table 94. ESPI State Register (ESPISTATE)
PS028702-1210
Bits
6
5
4
3
2
1
0
Bits
Field
RESET
R/W
ADDR
ESPI State Register
Description (Continued)
TUND – Transmit Underrun
0 = A Transmit Underrun error has not occurred.
1 = A Transmit Underrun error has occurred.
COL – Collision
0 = A Multi-Master collision (mode fault) has not occurred.
1 = A Multi-Master collision (mode fault) has been detected.
ABT – Slave mode transaction abort
This bit is set if the ESPI is configured in Slave mode, a transaction is occurring and SS deas-
serts before all bits of a character have been transferred as defined by the NUMBITS field of
the ESPIMODE Register. This bit is also be set in Slave mode by an SCK monitor timeout
(MMEN = 0, BRGCTL = 1).
0 = A Slave mode transaction abort has not occurred.
1 = A Slave mode transaction abort has been detected.
ROVR – Receive Overrun
0 = A Receive Overrun error has not occurred.
1 = A Receive Overrun error has occurred.
RDRF – Receive Data Register Full
0 = Receive Data Register is empty.
1 = Receive Data Register is full. A read from the ESPI (Receive) Data Register clears this bit.
TFST – Transfer Status
0 = No data transfer is currently in progress.
1 = Data transfer is currently in progress.
SLAS – Slave Select
Reading this bit returns the current value of the SS exclusive-OR’d with the SSPO bit.
0 = SS pin is Low, if SSPO = 0, SS pin is High if SSPO = 1 (SS is asserted).
1 = SS pin is High, if SSPO = 0, SS pin is Low if SSPO = 1 (SS is deasserted).
SCKI
R
7
0
The ESPI State Register (see Table 94) provides observability of the ESPI clock, data and
internal state.
SDI
R
6
0
5
P R E L I M I N A R Y
4
FF_E265H
Z16FMC Series Motor Control MCUs
3
ESPISTATE
Enhanced Serial Peripheral Interface
R
0
2
Product Specification
1
0
167