PIC16F636-I/P Microchip Technology Inc., PIC16F636-I/P Datasheet - Page 78

• Manufacturer Part Number: PIC16F636-I/P
• Description: 14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F636-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC12F635/PIC16F636/639
9.5
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up Timer (nominal 64 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• Brown-out
• Power glitch
• Software malfunction
TABLE 9-1:
DS41232B-page 76
0Bh/8Bh
0Ch
8Ch
9Ah
9Bh
9Ch
9Dh
Legend:
Note 1:
Address
Protection Against Spurious Write
INTCON
PIR1
PIE1
EEDAT
EEADR
EECON1
EECON2 EEPROM Control Register 2 (not a physical register)
x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the data EEPROM module.
PIC16F636/639 only.
Name
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
EEADR7
EEDAT7
Bit 7
EEIF
EEIE
GIE
—
(1)
EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
LVDIF
LVDIE
PEIE
Bit 6
—
CRIE
CRIF
Bit 5
T0IE
—
C2IE
C2IF
INTE
Preliminary
Bit 4
—
(1)
(1)
WRERR
RAIE
C1IE
Bit 3
C1IF
9.6
Data memory can be code-protected by programming
the CPD bit in the Configuration Word (Register 12-1)
to ‘0’.
When the data memory is code-protected, the CPU is
able to read and write data to the data EEPROM. It is
recommended to code-protect the program memory
when code-protecting data memory. This prevents
anyone from programming zeroes over the existing
code (which will execute as NOPs) to reach an added
routine, programmed in unused program memory,
which
Programming unused locations in program memory to
‘0’ will also help prevent data memory code protection
from becoming breached.
OSFIE
WREN
OSFIF
Bit 2
T0IF
outputs
Data EEPROM Operation During
Code Protection
Bit 1
INTF
WR
—
—
the
TMR1IF 0000 00-0 0000 00-0
TMR1IE 0000 00-0 0000 00-0
RAIF
contents
Bit 0
© 2005 Microchip Technology Inc.
RD
0000 0000 0000 0000
---- x000 ---- q000
---- ---- ---- ----
POR, BOD,
Value on
WUR
of
data
Value on
all other
Resets
memory.