PIC16F636-I/P Microchip Technology Inc., PIC16F636-I/P Datasheet - Page 123

• Manufacturer Part Number: PIC16F636-I/P
• Description: 14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F636-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.9
The PIC12F635/PIC16F636/639 has 8 sources of
interrupt:
• External Interrupt RA2/INT
• Timer0 Overflow Interrupt
• PORTA Change Interrupts
• 2 Comparator Interrupts
• Timer1 Overflow Interrupt
• EEPROM Data Write Interrupt
• Fail-Safe Clock Monitor Interrupt
The Interrupt Control register (INTCON) and Peripheral
Interrupt Request Register 1 (PIR1) record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in the
INTCON register and PIE1 register. GIE is cleared on
Reset.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
• INT Pin Interrupt
• PORTA Change Interrupt
• TMR0 Overflow Interrupt
The peripheral interrupt flags are contained in the
special register, PIR1. The corresponding interrupt
enable bit is contained in special register, PIE1.
The following interrupt flags are contained in the PIR1
register:
• EEPROM Data Write Interrupt
• 2 Comparator Interrupts
• Timer1 Overflow Interrupt
• Fail-Safe Clock Monitor Interrupt
When an interrupt is serviced:
• The GIE is cleared to disable any further interrupt.
• The return address is pushed onto the stack.
• The PC is loaded with 0004h.
© 2005 Microchip Technology Inc.
Interrupts
PIC12F635/PIC16F636/639
Preliminary
For external interrupt events, such as the INT pin or
PORTA change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 12-8). The latency is the same for one or two-
cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
For additional information on Timer1, comparators or
data EEPROM modules, refer to the respective
peripheral section.
12.9.1
External interrupt on RA2/INT pin is edge-triggered;
either rising if the INTEDG bit (OPTION<6>) is set, or
falling if the INTEDG bit is clear. When a valid edge
appears on the RA2/INT pin, the INTF bit (INTCON<1>)
is set. This interrupt can be disabled by clearing the
INTE control bit (INTCON<4>). The INTF bit must be
cleared in software in the Interrupt Service Routine
before re-enabling this interrupt. The RA2/INT interrupt
can wake-up the processor from Sleep if the INTE bit
was set prior to going into Sleep. The status of the GIE
bit decides whether or not the processor branches to the
interrupt vector following wake-up (0004h). See
Section 12.12 “Power-Down Mode (Sleep)” for details
on Sleep and Figure 12-10 for timing of wake-up from
Sleep through RA2/INT interrupt.
Note:
Note 1: Individual interrupt flag bits are set,
2: When an instruction that clears the GIE
RA2/INT INTERRUPT
The CMCON0 (19h) register must be
initialized to configure an analog channel
as a digital input. Pins configured as
analog inputs will read ‘0’.
regardless
corresponding mask bit or the GIE bit.
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
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DS41232B-page 121
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