PIC16F636-I/P Microchip Technology Inc., PIC16F636-I/P Datasheet - Page 110

• Manufacturer Part Number: PIC16F636-I/P
• Description: 14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F636-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC12F635/PIC16F636/639
REGISTER 11-6:
REGISTER 11-7:
DS41232B-page 108
bit 8
bit 7
bit 6-5
bit 4-1
bit 0
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 8
AUTOCHSEL: Auto Channel Select bit
1 = Enabled – AFE selects channel(s) that has demodulator output “high” at the end of T
0 = Disabled –
AGCSIG: Demodulator Output Enable bit, after the AGC loop is active
1 = Enabled – No output until AGC is regulating at around 20 mV
0 = Disabled – the AFE passes signal of any level it is capable of detecting
MODMIN<1:0>: Minimum Modulation Depth bit
00 = 50%
01 = 75%
10 = 25%
11 = 12%
LCZSEN<3:0>
0000 = -0dB (Default)
1111 = -30dB
R5PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
bit 8
COLPAR7: Set/Cleared so that this 8th parity bit + the sum of the config register row parity bits contain an odd number of
COLPAR6: Set/Cleared such that this 7th parity bit + the sum of the 7th bits in config registers 0 through 5 contain an odd
COLPAR5: Set/Cleared such that this 6th parity bit + the sum of the 6th bits in config registers 0 through 5 contain an odd
COLPAR4: Set/Cleared such that this 5th parity bit + the sum of the 5th bits in config registers 0 through 5 contain an odd
COLPAR3: Set/Cleared such that this 4th parity bit + the sum of the 4th bits in config registers 0 through 5 contain an odd
COLPAR2: Set/Cleared such that this 3rd parity bit + the sum of the 3rd bits in config registers 0 through 5 contain an odd
COLPAR1: Set/Cleared such that this 2nd parity bit + the sum of the 2nd bits in config registers 0 through 5 contain an odd
COLPAR0: Set/Cleared such that this 1st parity bit + the sum of the 1st bits in config registers 0 through 5 contain an odd
R6PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
Legend:
R = Readable bit
- n = Value at POR
Legend:
R = Readable bit
- n = Value at POR
AUTOCHSEL
COLPAR7
Note 1: Assured monotonic increment (or decrement) by design.
R/W-0
R/W-0
channel(s).
when the AGC begins regulating.
set bits.
number of set bits.
number of set bits.
number of set bits.
number of set bits.
number of set bits.
number of set bits.
number of set bits.
:
CONFIGURATION REGISTER 5 (ADDRESS: 0101)
COLUMN PARITY REGISTER 6 (ADDRESS: 0110)
COLPAR6
(1)
R/W-0
AFE
: LCZ Sensitivity Reduction bit
AGCSIG
R/W-0
follows channel enable/disable bits defined in Register 0
COLPAR5
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-0
MODMIN1
R/W-0
COLPAR4
R/W-0
Preliminary
MODMIN0
R/W-0
COLPAR3
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
LCZSEN3
R/W-0
COLPAR2
PP
R/W-0
LCZSEN2
at input pins. The AGC Active Status bit is set
R/W-0
COLPAR1
R/W-0
LCZSEN1
© 2005 Microchip Technology Inc.
R/W-0
STAB
x = Bit is unknown
x = Bit is unknown
; or otherwise, blocks the
COLPAR0
R/W-0
LCZSEN0
R/W-0
R6PAR
R/W-0
R5PAR
R/W-0
bit 0
bit 0