PIC16F636-I/P Microchip Technology Inc., PIC16F636-I/P Datasheet - Page 105

• Manufacturer Part Number: PIC16F636-I/P
• Description: 14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F636-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

11.32.2
The circuit executes 8 SPI commands from the MCU.
The command structure is:
Command (3 bits) + Configuration Address (4 bits) +
Data Byte and Row Parity Bit received by the AFE Most
Significant bit first. Table 11-5 shows the available SPI
commands.
TABLE 11-5:
© 2005 Microchip Technology Inc.
Command only – Address and Data are “Don’t Care”, but need to be clocked in regardless.
Read Command – Data will be read from the specified register address.
Write Command – Data will be written to the specified register address.
Command Address
Note:
000
001
010
011
100
101
110
111
COMMAND DECODER/
CONTROLLER
‘P’ denotes the row parity bit (odd parity) for the respective data byte.
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
0000
0001
0010
0011
0100
0101
0110
0111
0000
0001
0010
0011
0100
0101
0110
0111
SPI COMMANDS (AFE)
Column Parity
Column Parity
Config Byte 0
Config Byte 1
Config Byte 2
Config Byte 3
Config Byte 4
Config Byte 5
Config Byte 0
Config Byte 1
Config Byte 2
Config Byte 3
Config Byte 4
Config Byte 5
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
AFE Status
Not Used
Data
Parity
Row
P
P
P
P
P
P
P
X
P
P
P
P
P
P
P
X
X
X
X
X
X
X
PIC12F635/PIC16F636/639
Preliminary
Clamp on – enable modulation circuit
Clamp off – disable modulation circuit
Enter Sleep mode (any other command wakes the AFE)
AGC Preserve On – to temporarily preserve the current AGC level
AGC Preserve Off – AGC again tracks strongest input signal
Soft Reset – resets various circuit blocks
General – options that may change during normal operation
LCX antenna tuning and LFDATA output format
LCY antenna tuning
LCZ antenna tuning
LCX and LCY sensitivity reduction
LCZ sensitivity reduction and modulation depth
Column parity byte for Config Byte 0 -> Config Byte 5
AFE status – parity error, which input is active, etc.
General – options that may change during normal operation
LCX antenna tuning and LFDATA output format
LCY antenna tuning
LCZ antenna tuning
LCX and LCY sensitivity reduction
LCZ sensitivity reduction and modulation depth
Column parity byte for Config Byte 0 -> Config Byte 5
Register is readable, but not writable
The AFE operates in SPI mode 0,0. In mode 0,0 the
clock idles in the low state (Figure 11-19). SDI data is
loaded into the AFE on the rising edge of SCLK and
SDO data is clocked out on the falling edge of SCLK.
There must be multiples of 16 clocks (SCLK) while CS
is low or commands will abort.
Description
DS41232B-page 103