PIC16F636-I/P Microchip Technology Inc., PIC16F636-I/P Datasheet - Page 37

• Manufacturer Part Number: PIC16F636-I/P
• Description: 14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F636-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.5
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bit.
3.5.1
The System Clock Select (SCS) bit (OSCCON<0>)
selects the system clock source that is used for the
CPU and peripherals.
When SCS = 0, the system clock source is determined
by configuration of the FOSC<2:0> bits in the
Configuration Word register (Register 12-1).
When SCS = 1, the system clock source is chosen by
the internal oscillator frequency selected by the IRCF
bits. After a Reset, SCS is always cleared.
3.5.2
The Oscillator Start-up Time-out Status (OSTS) bit
(OSCCON<3>) indicates whether the system clock is
running from the external clock source, as defined by
the FOSC bits, or from the internal clock source. In
particular, OSTS indicates that the Oscillator Start-up
Timer (OST) has timed out for LP, XT or HS modes.
3.6
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up time
from the time spent awake and can reduce the overall
power consumption of the device.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the INTOSC as
the clock source and go back to Sleep without waiting
for the primary oscillator to become stable.
© 2005 Microchip Technology Inc.
Note:
Note:
Clock Switching
Two-Speed Clock Start-up Mode
SYSTEM CLOCK SELECT (SCS) BIT
Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-
Safe Clock Monitor, does not update the
SCS bit. The user can monitor the OSTS
(OSCCON<3>) to determine the current
system clock source.
OSCILLATOR START-UP TIME-OUT
STATUS BIT
Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit (OSCCON<3>) to remain
clear.
PIC12F635/PIC16F636/639
Preliminary
When the PIC12F635/PIC16F636/639 is configured for
LP, XT or HS modes, the Oscillator Start-up Timer
(OST) is enabled (see Section 3.3.1 “Oscillator Start-
up Timer (OST)”). The OST timer will suspend
program execution until 1024 oscillations are counted.
Two-Speed Start-up mode minimizes the delay in code
execution by operating from the internal oscillator as
the OST is counting. When the OST count reaches
1024 and the OSTS bit (OSCCON<3>) is set, program
execution switches to the external oscillator.
3.6.1
Two-Speed Start-up mode is configured by the
following settings:
• IESO = 1 (CONFIG<10>) Internal/External
• SCS = 0.
• FOSC configured for LP, XT or HS mode.
• Two-Speed Start-up mode is entered after:
• Power-on Reset (POR) and, if enabled, after
• Wake-up from Sleep.
If the external clock oscillator is configured to be
anything other than LP, XT or HS mode, then Two-
Speed Start-up is disabled. This is because the external
clock oscillator does not require any stabilization time
after POR or an exit from Sleep.
3.6.2
The Two-Speed Start-up sequence is listed below.
1.
2.
3.
4.
5.
6.
7.
3.6.3
Checking the state of the OSTS bit (OSCCON<3>) will
confirm if the PIC12F635/PIC16F636/639 is running
from the external clock source, as defined by the FOSC
bits in the Configuration Word register (Register 12-1)
or the internal oscillator.
Switchover bit.
PWRT has expired, or
Wake-up from Power-on Reset or Sleep.
Instructions begin execution by the internal
oscillator at the frequency set in the IRCF bits
(OSCCON<6:4>).
OST enabled to count 1024 clock cycles.
OST timed out, wait for falling edge of the
internal oscillator.
OSTS is set.
System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
System clock is switched to external clock
source.
TWO-SPEED START-UP MODE
CONFIGURATION
TWO-SPEED START-UP
SEQUENCE
CHECKING EXTERNAL/INTERNAL
CLOCK STATUS
DS41232B-page 35