PIC16F636-I/P Microchip Technology Inc., PIC16F636-I/P Datasheet - Page 20

• Manufacturer Part Number: PIC16F636-I/P
• Description: 14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F636-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC12F635/PIC16F636/639
TABLE 2-5:
DS41232B-page 18
Addr
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah PCLATH
8Bh INTCON
8Ch PIE1
8Dh
8Eh PCON
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
9Bh
99h
9Ah EEDAT
9Bh EEADR
9Ch EECON1
9Dh EECON2
9Eh
9Fh
Legend:
Note 1:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISC
OSCCON
OSCTUNE
LVDCON
WPUDA
IOCA
WDA
VRCON
2:
3:
Name
(2)
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
RA3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register.
MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set
again if the mismatch exists.
—
—
—
—
—
—
—
—
—
—
(2)
PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addressing this location uses contents of FSR to address data memory
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
EEPROM Control Register 2 (not a physical register)
(not a physical register)
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
Unimplemented
Unimplemented
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
RAPU
VREN
EEIE
Bit 7
IRP
GIE
—
—
—
—
—
—
—
—
—
—
—
INTEDG
LVDIE
IRCF2
Bit 6
PEIE
RP1
—
—
—
—
—
—
—
—
—
—
—
ULPWUE SBODEN
WPUDA5 WPUDA4
TRISC5
TRISA5
IOCA5
IRCF1
IRVST
WDA5
T0CS
CRIE
Bit 5
T0IE
VRR
RP0
—
—
—
Write Buffer for upper 5 bits of Program Counter
TRISA4
TRISC4
LVDEN
IRCF0
IOCA4
WDA4
TUN4
T0SE
Bit 4
INTE
C2IE
Preliminary
TO
—
—
WRERR
TRISC3
TRISA3
IOCA3
OSTS
TUN3
WUR
RAIE
C1IE
Bit 3
PSA
VR3
PD
—
—
—
WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111
TRISA2
TRISC2
OSFIE
LVDL2
IOCA2
WREN
WDA2
TUN2
Bit 2
T0IF
HTS
PS2
VR2
—
Z
TRISA1
TRISC1
IOCA1
LVDL1
WDA1
TUN1
Bit 1
INTF
POR
VR1
PS1
LTS
WR
DC
—
TMR1IE 0000 00-0 0000 00-0
TRISA0 --11 1111 --11 1111
TRISC0 --11 1111 --11 1111
RAIF
LVDL0
IOCA0
WDA0
TUN0
© 2005 Microchip Technology Inc.
Bit 0
BOD
SCS
PS0
VR0
RD
C
(3)
xxxx xxxx xxxx xxxx
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
---0 0000 ---0 0000
0000 0000 0000 0000
--01 q-qq --0u u-uu
-110 q000 -110 x000
---0 0000 ---u uuuu
--00 -000 --00 -000
--00 0000 --00 0000
--11 -111 --11 -111
0-0- 0000 0-0- 0000
---- x000 ---- q000
---- ---- ---- ----
POR/BOD/
Value on
WUR
—
—
—
—
—
—
—
—
—
—
Value on
Resets
all other
—
—
—
—
—
—
—
—
—
—
(1)