PIC16F636-I/P Microchip Technology Inc., PIC16F636-I/P Datasheet - Page 39

• Manufacturer Part Number: PIC16F636-I/P
• Description: 14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F636-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.7.1
The Fail-Safe condition is cleared after a Reset, the
execution of a SLEEP instruction, or a modification of the
SCS bit. While in Fail-Safe condition, the PIC12F635/
PIC16F636/639 uses the internal oscillator as the
system clock source. The IRCF bits (OSCCON<6:4>)
can be modified to adjust the internal oscillator
frequency without exiting the Fail-Safe condition.
FIGURE 3-9:
3.7.2
The FSCM is designed to detect oscillator failure at any
point after the device has exited a Reset or Sleep
condition and the Oscillator Start-up Timer (OST) has
expired. If the external clock is EC or RC mode,
monitoring will begin immediately following these
events.
For LP, XT or HS mode, the external oscillator may
require a start-up time considerably longer than the
FSCM sample clock time or a false clock failure may be
detected (see Figure 3-9). To prevent this, the internal
oscillator is automatically configured as the system
clock and functions until the external clock is stable (the
OST has timed out). This is identical to Two-Speed
Start-up mode. Once the external oscillator is stable,
the LFINTOSC returns to its role as the FSCM source.
© 2005 Microchip Technology Inc.
Note:
Sample Clock
CM Output
FAIL-SAFE CONDITION CLEARING
RESET OR WAKE-UP FROM SLEEP
OSCFIF
System
Output
Clock
The system clock is normally at a much higher frequency than the sample clock. The relative
frequencies in this example have been chosen for clarity.
(Q)
FSCM TIMING DIAGRAM
CM Test
PIC12F635/PIC16F636/639
Preliminary
The Fail-Safe condition must be cleared before the
OSFIF flag can be cleared.
Note:
CM Test
Oscillator
Failure
Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit (OSCCON<3>) to verify the
oscillator start-up and system clock
switchover has successfully completed.
Detected
Failure
CM Test
DS41232B-page 37