PIC16F636-I/P Microchip Technology Inc., PIC16F636-I/P Datasheet - Page 118

• Manufacturer Part Number: PIC16F636-I/P
• Description: 14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F636-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC12F635/PIC16F636/639
12.7
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired, then
OST is activated after the PWRT time-out has expired.
The total time-out will vary based on oscillator
configuration and PWRTE bit status. For example, in EC
mode with PWRTE bit erased (PWRT disabled), there
will be no time-out at all. Figure 12-4, Figure 12-5 and
Figure 12-6 depict time-out sequences. The device can
execute code from the INTOSC, while OST is active, by
enabling Two-Speed Start-up or Fail-Safe Clock Monitor
(See Section 3.6.2 “Two-Speed Start-up Sequence”
and Section 3.7 “Fail-Safe Clock Monitor”).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 12-5). This is useful for testing purposes or
to synchronize more than one PIC12F635/PIC16F636/
639 device operating in parallel.
Table 12-5 shows the Reset conditions for some
special registers, while Table 12-4 shows the Reset
conditions for all the registers.
TABLE 12-1:
TABLE 12-2:
DS41232B-page 116
XT, HS, LP
RC, EC, INTOSC
03h
8Eh
Legend:
Note 1:
Address
Configuration
Oscillator
Time-out Sequence
STATUS
PCON
u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are
not used by BOD.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
Name
TIME-OUT IN VARIOUS SITUATIONS
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT DETECT
T
Bit 7
PWRT
IRP
—
PWRTE = 0
+ 1024 • T
T
PWRT
Bit 6
RP1
—
Power-up
ULPWUE SBODEN
OSC
Bit 5
RP0
PWRTE = 1
1024 • T
Bit 4
—
TO
Preliminary
OSC
WUR
Bit 3
PD
T
PWRT
12.8
The Power Control register, PCON (address 8Eh), has
two Status bits to indicate what type of Reset that last
occurred.
Bit 0 is BOD (Brown-out). BOD is unknown on Power-
on Reset. It must then be set by the user and checked
on subsequent Resets to see if BOD = 0, indicating that
a Brown-out has occurred. The BOD Status bit is a
“don’t care” and is not necessarily predictable if the
brown-out circuit is disabled (BODEN<1:0> = 00 in the
Configuration Word register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., V
gone too low).
For more information, see Section 4.2.3 “Ultra Low-
Power Wake-up” and Section 12.6 “Brown-out
Detect (BOD)”.
PWRTE = 0
Bit 2
—
Z
+ 1024 • T
T
PWRT
Brown-out Detect
Power Control (PCON) Register
Bit 1
POR
DC
OSC
Bit 0
BOD
C
PWRTE = 1
1024 • T
© 2005 Microchip Technology Inc.
0001 1xxx
--01 q-qq
POR, BOD,
—
Value on
WUR
OSC
DD
1024 • T
from Sleep
000q quuu
--0u u-uu
Wake-up
Resets
Value on
all other
may have
—
OSC
(1)