MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 929

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

RISC Microcode from RAM
C.4.2 Performance
At 25Mhz, an aggregate Asynchronous HDLC bandwidth of 3 Mbps divided among the 4
SCCs consumes 100% of the processing power of the RISC communications engine. If only
a percentage of the total available Asynchronous HDLC bandwidth is used, the remaining
RISC processing power can be used to run other protocols on other channels. Table C-4
shows the AHDLC configuration
C.5 PROFIBUS CONTROLLER
Process field bus (PROFIBUS) is a UART- based master slave protocol that specific data
between 9.6 kbps to 1.525 Mbps. The PROFIBUS protocol is mainly used in industrial pro-
cess control applications. The protocol is defined in the German DIN standard 19 245.
The PROFIBUS microcode running on the QUICC RISC controller assists the core in han-
dling some of the time-critical PROFIBUS link layer functions, leaving more of the core avail-
able for the application software.
C.5.1 Key Features
C-7
• Reception of frames with only one “shared” flag.
• Automatic generation and stripping of transparency characters according to the Internet
• Automatic transmission of the ABORT sequence (0x7D,0x7E) after the STOP TRANS-
• Automatic transmission of IDLE characters between frames and characters.
• Consumes 768 bytes of the QUICC’s internal memory.
• Frame preceding IDLE sequence generation/checking
• Flexible Frame Oriented Data Buffers
• Separate interrupts for Frames and Buffers (Receive and Transmit)
• Maintenance of six 16-bit error counters
• Two Address Comparison Registers with Mask
• Frame Error, Noise Error, Parity Error Detection
• Detection of IDLE in middle of a frame
• Check Sum generation/checking
Engineering Task Force RFC 1549 utilizing transmit and receive control character
maps.
MIT command is issued.
AHDLC Channels
1 x 115 Kbit/s
2 x 230 Kbit/s
3 x 230 Kbit/s
Freescale Semiconductor, Inc.
Risc Bandwidth
Consumed (est)
For More Information On This Product,
Table C-4. AHDLC Configuration
15%
24%
4%
MC68360 USER’S MANUAL
Go to: www.freescale.com
1 x 10Mbit Ethernet, 2 x 1.5 Mbit HDLC, 9.6 Kbit SMC UART
1 x 10Mbit Ethernet, 1 x 1.5 Mbit HDLC, 9.6 Kbit SMC UART
1 x 5Mbit HDLC, 2 x 9.6 Kbit SMC UART
Possible Configuration of Other Channels
MOTOROLA