MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 342

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Timers
7.5.2 General-Purpose Timer Units
The clock input to the prescaler may be selected from three sources: the general system
clock, the general system clock divided by 16, or the corresponding TINx pin. Each option
is discussed in the following paragraphs.
The general system clock is generated in the clock synthesizer and defaults to the system
frequency (for instance, 25 MHz). However, the general system clock has the option to be
divided before it leaves the clock synthesizer. This mode, called slow go, is used to save
power. Whatever the resulting frequency of the general system clock, the user may choose
either that frequency or that frequency divided by 16 as the input to the prescaler of each
timer.
Alternatively, the user may choose the TINx pin to be the clock source. TINx is internally syn-
chronized to the internal clock. If the user has chosen to internally cascade two 16-bit timers
to a 32-bit timer, then a timer may internally use the clock generated by the output of another
timer.
The clock input source is selected by the ICLK bits of the corresponding TMR. The prescaler
is programmed to divide the clock input by values from 1 to 256. The output of the prescaler
is used as an input to the 16-bit counter.
The best resolution of the timer is one clock cycle (40 ns at 25 MHz). The maximum period
(when the reference value is all ones) is 268,435,456 cycles (10.7 sec at 25 MHz). Both val-
ues assume that the general system clock is the full 25 MHz.
Each timer may be configured to count until a reference is reached and then either begin a
new time count immediately or continue to run. The FRR bit of the corresponding TMR
selects each mode. Upon reaching the reference value, the corresponding TER bit is set,
and an interrupt is issued if the ORI bit in the TMR is set.
Each timer may output a signal on the timer output pin (TOUT1, TOUT2, TOUT3, or TOUT4)
when the reference value is reached (selected by the OM bit of the corresponding TMR).
This signal can be an active-low pulse or a toggle of the current output. The output can also
be internally connected to the input of another timer, resulting in a 32-bit timer.
Each timer has a 16-bit TCR, which is used to latch the value of the counter when a defined
transition of TIN1, TIN2, TIN3, or TIN4 is sensed by the corresponding input capture edge
detector. The type of transition triggering the capture is selected by the CE bits in the corre-
sponding TMR. Upon a capture or reference event, the corresponding TER bit is set, and a
maskable interrupt request is issued to the CPM interrupt controller.
7-18
• Input Capture Capability
• Output Compare with Programmable Mode for the Output Pin
• Two Timers Internally or Externally Cascadable To Form a 32-Bit Timer
• Free Run and Restart Modes
• Functionally Compatible with Timer 1 and Timer 2 on the MC68302
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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