MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 775

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Applications
The SCSI bus has a total of 18 signals—9 are used for control, and 9 are used for data (one
parity bit). The bidirectional data lines transfer data, commands, status, and message infor-
9-55
DB0–DB7
Signal
MSG
REQ
DBP
ATN
BSY
ACK
RST
SEL
C/D
I/O
Initiator/Target 8-Bit Bidirectional Data Bus.
Initiator/Target Data-Bus Parity Line. Optional.
Initiator/Target Busy. Indicates that the bus is unavailable for use.
Any Device
Driven By
SCSI
Initiator
Initiator
Initiator
Target
Target
Target
Target
ACK
Attention. Used to send a message to the target when it controls the bus.
Acknowledge. Used by the initiator for handshaking.
Reset. Used to initiate a bus-free phase.
Driven by the target to indicate that the current transfer is a message.
Select. Used by the initiator to select a target before command execution. Also used
by the target to reconnect when the reselection phase is implemented.
Control/Data. Used during the information transfer phases to transfer commands, sta-
tus, data or messages over the bus.
Request. Used by the target during information transfer phases.
Input/Output. Determines the direction of the transfer.
Freescale Semiconductor, Inc.
For More Information On This Product,
ATN
Figure 9-17. SCSI Bus Signals
Table 9-1. SCSI Bus Signals
SEL
MC68360 USER’S MANUAL
Go to: www.freescale.com
HOST BUS ADAPTER (53C90)
HOST PROCESSOR (QUICC)
RST
DISK CONTROLLER
BSY
DISK
C/D
HOST BUS
Signal Explanation
I/O
REQ
MSG
DATA
LINES
BUS
MOTOROLA