MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 688

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Parallel I/O Ports
For each ODx bit, the definition is as follows:
7.14.7.2 PORT B DATA REGISTER (PBDAT). A read of PBDAT returns the data at the
pin, independent of whether the pin is defined as an input or an output. This allows detection
of output conflicts at the pin by comparing the written data with the data on the pin. A write
to the PBDAT is latched, and if that bit in the PBDIR is configured as an output, the value
latched for that bit will be driven onto its respective pin. PBDAT can be read or written at any
time. PBDAT is not initialized and is undefined at reset.
7.14.7.3 PORT B DATA DIRECTION REGISTER (PBDIR). PBDIR is cleared at system
reset.
For each DRx bit, the definition is as follows:
7.14.7.4 PORT B PIN ASSIGNMENT REGISTER (PBPAR). PBPAR is cleared at system
reset.
7-364
DR15
DD15
D15
15
15
15
0 = The I/O pin is actively driven as an output.
1 = The I/O pin is an open-drain driver. As an output, the pin is actively driven low, but
0 = The corresponding pin is an input.
1 = The corresponding pin is an output.
DR14
DD14
D14
14
14
14
is three-stated otherwise.
DR13
DD13
D13
13
13
13
SMTxD1, DONE1 and DONE2 can not be set as open drain driv-
er regardless of the setting of this register.
DR12
DD12
D12
12
12
12
DR11
DD11
D11
11
11
11
Freescale Semiconductor, Inc.
For More Information On This Product,
DR10
DD10
D10
10
10
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
DR9
DD9
D9
9
9
9
DR8
DD8
D8
NOTE
8
8
8
DR7
DD7
D7
7
7
7
DR6
DD6
D6
6
6
6
DR5
DD5
D5
5
5
5
DR4
DD4
D4
4
4
4
DR3
DD3
D3
3
3
3
DR2
DD2
D2
2
2
2
MOTOROLA
DR17
DD17
D17
DR1
DD1
D1
17
17
17
1
1
1
DR16
DD16
D16
DR0
DD0
D0
16
16
16
0
0
0