MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 492

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
7-168
9. Write RBASE and TBASE in the SCC parameter RAM to point to the Rx BD and Tx
10. Program the CR to execute the INIT RX & TX PARAMS command for this channel.
11. Write RFCR with $15 and TFCR with $15 for normal operation.
12. Write MRBLR with the maximum number of bytes per receive buffer. For this case,
13. Write MAX_IDL with $0000 in the SCC UART-specific parameter RAM to disable
14. Set BRKCR to $0001, so that if a STOP TRANSMIT command is issued, one break
15. Clear PAREC, FRMEC, NOSEC, and BRKEC in the SCC UART-specific parameter
16. Clear UADDR1 and UADDR2. They are not used.
17. Clear TOSEQ. It is not used.
18. Write CHARACTER1–8 with $8000. They are not used.
19. Write RCCM with $C0FF. It is not used.
20. Initialize the Rx BD. Assume the Rx data buffer is at $00404000 in main memory.
21. Initialize the Tx BD. Assume the Tx data buffer is at $00404100 in main memory
22. Write $FFFF to the SCCE to clear any previous events.
23. Write $0003 to the SCCM to enable the TX and RX interrupts.
24. Write $08000000 to the CIMR to allow SCC4 to generate a system interrupt. (The
25. Write $00000020 to GSMR_H4 to configure a small receive FIFO width.
26. Write $00028004 to GSMR_L4 to configure 16 sampling for transmit and receive,
27. Set the PSMR4 to $B000 to configure automatic flow control using the CTS pin,
28. Write $00028034 to GSMR_L4 to enable the SCC4 transmitter and receiver. This
SICR.
BD in the dual-port RAM. Assuming one Rx BD at the beginning of dual-port RAM and
one Tx BD following that Rx BD, write RBASE with $0000 and TBASE with $0008.
For instance, to execute this command for SCC1, write $0001 to the CR. This com-
mand causes the RBPTR and TBPTR parameters of the serial channel to be updated
with the new values just programmed into RBASE and TBASE.
assume 16 bytes, so MRBLR = $0010.
the MAX_IDL functionality for this example.
character will be sent.
RAM for the sake of clarity.
Write $B000 to Rx_BD_Status. Write $0000 to Rx_BD_Length (not required—done
for instructional purposes only). Write $00404000 to Rx_BD_Pointer.
and contains five 8-bit characters. Write $B000 to Tx_BD_Status. Write $0010 to
Tx_BD_Length. Write $00404100 to Tx_BD_Pointer.
CICR should also be initialized.)
the CTS and CD pins to automatically control transmission and reception (DIG bits),
and the UART mode. Notice that the transmitter (ENT) and receiver (ENR) have
not been enabled yet.
8-bit characters, no parity, 1 stop bit, and asynchronous UART operation.
additional write ensures that the ENT and ENR bits will be enabled last.
Freescale Semiconductor, Inc.
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MC68360 USER’S MANUAL
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