MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 143

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
SECTION 5
CPU32+
The CPU32+, the second instruction processing module of the M68300 family, is based on
the industry-standard MC68000 core processor. Like the original CPU32, it has many fea-
tures of the MC68010 and MC68020 as well as unique features suited for high-performance
processor applications. The CPU32+ provides a significant performance increase over the
MC68000 CPU, yet maintains source-code and binary-code compatibility with the M68000
family.
The CPU32+ differs from the original CPU32 in two ways: it allows an option of a 32-bit data
interface and allows byte-misaligned accesses to data operands.
5.1 OVERVIEW
The CPU32+ is designed to interface to the intermodule bus (IMB), allowing interaction with
other IMB submodules. In this manner, integrated processors can be developed that contain
useful peripherals on chip. This integration provides high-speed accesses among the IMB
submodules, increasing system performance.
The CPU32+ core is a CPU32 core with its bus interface unit modified to connect directly to
the 32-bit IMB and take advantage of the larger bus width. Although the original CPU32 core
already had a 32-bit internal data path and 32-bit arithmetic hardware, its external interface
(i.e., to the internal IMB) was 16 bits. The CPU32+ core, however, can operate on 32-bit
external operands with one bus cycle. This capability allows the CPU32+ core to fetch a
long-word instruction or two word-length instructions in one bus cycle, allowing the internal
instruction queue to be filled more quickly. The CPU32+ core can also read and write 32-
bits of data in one bus cycle. The CPU32+ has an additional word in its instruction pipeline
when fetching from a 32-bit port. When fetching from a 16-bit port, this additional word is
disabled. The performance of the CPU32+ on a 16-bit bus is the same as the CPU32 per-
formance.
The CPU32+ also supports byte-misaligned operands. Since operands can reside at any
byte boundary, they may occasionally become misaligned. A byte operand is properly
aligned at any address; a word operand is misaligned at a odd address; a long-word oper-
and is misaligned at an address that is not evenly divisible by four. Devices such as the
MC68302, MC68000/8, MC68010, and CPU32-based MC68300 allow long-word operand
transfers at odd-word addresses, but force exceptions if word or long-word operand trans-
fers are attempted at odd-byte addresses. Although the CPU32+ does not enforce any align-
ment restrictions for data operands (including PC relative data addresses), some
performance degradation occurs when additional bus cycles are required for long-word or
word operands that are misaligned. For maximum performance, data items should be
MOTOROLA
MC68360 USER’S MANUAL
5-1
For More Information On This Product,
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