Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 70
Z85C3010PSG
Manufacturer Part Number
Z85C3010PSG
Description
IC 10MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3010PSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3934
Z85C3010PSG
Z85C3010PSG
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Manufacturer
Quantity
Price
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Part Number:
Z85C3010PSG
Manufacturer:
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UM010901-0601
3.4.2 DPLL Operation in the FM Modes
To operate in FM mode, the DPLL must be supplied with a
clock that is 16 times the data rate. The DPLL uses this
clock, along with the receive data, to construct, receive,
and transmit clock outputs that are phased to receive and
transmit data properly.
RX DPLL Out
TX DPLL Out
Correction
Correction
Windows
Receive
Length
Output
Bit Cell
Count
DPLL
Count
Data
+1
32
16
No Change
17
+1
-1
18 19 20
32
+1
Figure 3-7. DPLL Operating Example (NRZI Mode)
-1
21 22 23 24 25 26 27 28 29 30 31
32
Figure 3-8. DPLL Operation in the FM Mode
+1
-1
31
+1
-1
31
+1
In FM mode, the counter in the DPLL counts from 0 to 31,
but now each cycle corresponds to 2-bit cells. To make
adjustments to remain in phase with the receive data, the
DPLL divides a pair of bit cells into five regions, making the
adjustment to the counter dependent upon which region the
transition on the receive data input occurred (Figure 3-8).
31
-1
Ignored
+1
0
1
33
-1
2
3
+1
SCC/ESCC Ancillary Support Circuitry
4 5
33
-1
6
SCC™/ESCC™ User’s Manual
+1
7
33
8
-1
9
+1
10
11
No Change
12 13 14
+1
15
3-9
3
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