Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 55

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.5 BLOCK/DMA TRANSFER (Continued)
2.5.2 DMA Requests
The two DMA request pins /W//REQ and /DTR//REQ can
be programmed for DMA requests. The /W//REQ pin is
used as either a transmit or a receive request, and the
/DTR//REQ pin can be used as a transmit request only. For
full-duplex operation, the /W//REQ is used for receive, and
the /DTR//REQ is used for transmit. These modes are de-
scribed below.
2.5.2.1 DMA Request on ESCC
Transmit DMA request is also affected by WR7' bit D5. As
noted earlier, WR7' D5 affects both the transmit interrupt
and DMA request generation similarly.
Note: WR7' D3 is ignored by the Receive Request
function. This allows a DMA to transfer all bytes out of the
Receive FIFO and still maintain the full advantage of the
FIFO when the DMA has a long latency response
acquiring the data bus.
Bit D5 of WR7' is set to 1 after reset to maintain maximum
compatibility with SCC designs. This is necessary because
if WR7' D5=0 when the request function is enabled, re-
quests are made in rapid succession to fill the FIFO. Conse-
quently, some designs which require an edge to be detected
for each data transfer may not recover fast enough to detect
the edges. This is handled by programming WR7' D5=1, or
changing the DMA to be level sensitive instead of edge sen-
sitive. Programming WR7' D5=0 has the advantage of the
DMA requesting to keep the FIFO full. Therefore, if the CPU
is busy, a significantly longer latency can be tolerated with-
out the transmitter under-running.
2-36
(/DTR//REQ)
(/W//REQ)
/TRxC
PCLK
/REQ
/REQ
Figure 2-28. Transmit Request Assertion
2.5.2.2 DMA Request On Transmit (using /W//REQ)
The Request On Transmit function is selected by setting
D6 of WR1 to 1, D5 of WR1 to 0, and then enabling the
function by setting D7 of WR1 to 1. In this mode, the
/W//REQ pin carries the /REQ signal, which is active Low.
When this mode is selected but not yet enabled, the
/W//REQ is driven High.
The /REQ pin generates a falling edge for each byte writ-
ten to the transmit buffer when the DMA controller is to
write new data. For the Z80X30, the /REQ pin then goes
inactive on the falling edge of the DS that writes the new
data (see AC spec #26, TdDSf(REQ)) For the Z85X30, the
/REQ pin then goes inactive on the falling edge of the WR
strobe that writes the new data (see AC spec #33, Td-
WRf(REQ)) This is shown in Figure 2-28.
Note: The /REQ pin follows the state of the transmit buffer
even though the transmitter is disabled. Thus, if the /REQ
is enabled, the DMA writes data to the SCC before the
transmitter is enabled. This will not cause a problem in
Asynchronous mode, but it may cause problems in
Synchronous mode because the SCC sends data in
preference to flags or sync characters. It may also
complicate the CRC initialization, which cannot be done
until after the transmitter is enabled.
On the ESCC, this complication can be avoided in SDLC
mode by using the Automatic SDLC Opening Flag Trans-
mission feature and the Auto EOM reset feature, which
also resets the transmit CRC (see Section 4.4.1 for de-
tails). Applications using other synchronous modes should
enable the transmitter before enabling the /REQ function.
ASYNC Modes
SYNC Modes
UM010901-06
01