Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 233
Z85C3010PSG
Manufacturer Part Number
Z85C3010PSG
Description
IC 10MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3010PSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3934
Z85C3010PSG
Z85C3010PSG
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Application Note
Serial Communication Controller (SCC
RECEIVE INTERRUPTS ON FIRST CHARACTER OR SPECIAL CONDITIONS
The sequence of events in this mode is similar to that in
“Receive Interrupts on all received characters and Special
Conditions”, except that it generates Receive Character
Interrupt on the first received character only, and
subsequent data is read by the DMA.
The SCC is placed in this mode by programming Bit D4-3
of WR1 to 01. Once programmed in this mode, the SCC
6-98
Figure 3. Typical SDLC Receive Sequence with Receive Interrupts on First Character or Special Condition
™
): SDLC Mode of Operation
generates interrupts when it receives the First Character of
the packet or a Special Condition occurs. This mode is for
operation with the DMA. On the interrupt for the first
received character, DMA is enabled. On Special
Conditions (either End-of-Message, overrun, or Parity
error, — parity on the SDLC is not normal, however), the
service routine stops the DMA and starts over again.
UM010901-0601
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