Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 143

IC 10MHZ Z8500 CMOS SCC 40-DIP

Z85C3010PSG

Manufacturer Part Number
Z85C3010PSG
Description
IC 10MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Series
SCCr
Datasheets

Specifications of Z85C3010PSG

Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3934
Z85C3010PSG

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Application Note
Interfacing Z80
Z80B CPU TO Z8500A PERIPHERALS
No additional Wait states are necessary during I/O cycles,
although Wait states can be inserted to compensate for
any systems delays. Although the Z80B timing parameters
indicate a negative value for data valid prior to /WR, this is
a worse than “worst case” value. This parameter is based
upon the longest (worst case) delay for data available from
the falling edge of the CPU clock minus the shortest (best
case) delay for CPU clock High to /WR Low. The negative
value resulting from these two parameters does not occur
because the worst case of one parameter and best case of
the other do not occur within the same device. This
indicates that the value for data available prior to /WR will
always be greater than zero.
All setup and pulse width times for the Z8500A peripherals
are met by the standard Z80B timing. In determining the
interface necessary, the /CE signal to the Z8500A
peripherals is assumed to be the decoded address
qualified with /IORQ signal.
6-8
®
CPUs to the Z8500 Peripheral Family
Figure 5. Z80B CPU to Z8500A Peripheral Minimum I/O Cycle Timing
Figure 5 shows the minimum Z80B CPU to Z8500A
peripheral interface timing for I/O cycles. If additional Wait
states are needed, the same number of Wait states can be
inserted for both I/O Read and I/O Write cycles in order to
simplify interface logic. There are several ways to place
the Z80B CPU into a Wait condition (such as counters or
shift registers to count system clock pulses), depending
upon whether or not the user wants to place Wait states in
all I/O cycles, or only during Z8500A I/O cycles. Tables 6
and 7 list the Z8500A peripheral and Z80B CPU timing
parameters (respectively) of concern during the I/O cycles.
Tables 8 and 9 list the equations used in determining if
these parameters are satisfied. In generating these
equations and the values obtained from them, the required
number of Wait states was taken into account. The
reference numbers in Tables 6 and 7 refer to the timing
diagram of Figure 5.
UM010901-0601

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