Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 235

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

Application Note
Serial Communication Controller (SCC
RECEIVE INTERRUPTS ON SPECIAL CONDITIONS ONLY
The sequence of event in this mode is similar to that for
“Receive Interrupts on first received character or Special
Condition,” except it will not generate Receive Character
Available interrupt at all. This mode is designed for
operations where the DMA is pre-programmed, or the
application does not have enough time to set up DMA
transfer on First Character interrupt.
The SCC is placed in this mode by programming Bit D4-3
of WR1 to 11. Once programmed in this mode, the SCC
generates interrupts when Special Conditions occur. On
Special
overrun/Parity error, if enabled), corrective action can be
taken for that packet.
The SDLC Frame Status Buffer (not available on the
NMOS version) is very useful in this mode. First of all, set
RECEIVING BACK TO BACK FRAME IN RECEIVE INTERRUPTS ON SPECIAL CONDITION
ONLY MODE
“Back to Back” frame means there are two frames
separated with only one flag — the closing flag of the
previous packet also acts as the opening flag of the
following packet. Receiving such packets is identical to
receiving a single packet, except that the sequence of
events happens in a short time around the shared flag.
Assuming SCC is running under Receive Interrupts on
Special Condition only mode (under DMA Control), a
typical sequence of events is shown in Figure 4. It is
identical to that used for “Receive Interrupts on Special
Condition Only” mode, with the addition of another
following packet.
Notes on Figure 4:
1. DMA request data before 0FFH.
2. DMA request for data 0FFH.
3. DMA request for data 42H.
4. DMA request for the first CRC byte. The SCC treats
5. DMA request for the second CRC byte. The closing
6. This interrupt is EOF (End of Frame), a Special
6-100
the CRC as data, since the SCC does not yet
distinguish a difference between CRC and data!
flag is recognized two bit-times before the second
CRC byte is completely assembled in the Receive
Shift Register. As soon as it is transferred to the
Receive Buffer, it generates a DMA request.
Condition Interrupt. This will not occur until the DMA
has read the 2nd CRC byte from the Receive Buffer.
When it occurs the Receive Buffer is locked and no
more DMA requests can be generated until the
Condition
(either
End-Of-Message
™
): SDLC Mode of Operation
or
DMA to transfer several packets. The SDLC Frame Status
Buffer holds information which tells you how many bytes
were in the received packet and reports whether or not
error conditions (overrun/CRC error/parity error) have
occurred.
The sequence of events in this mode is identical to the
“Receive Interrupts on First Character or Special
Condition” mode (Figure 3); Note 3, however, does not
apply, and Note 4 should read as follows for this case:
Note 4 in Receive Interrupts on Special Condition only
mode:
DMA request for data 81H. The DMA function of the SCC
should be enabled by this time frame.
7. DMA request for second CRC byte. This occurs when
8. DMA request for data 01H.
9. MA request for data 03H.
Receive Buffer is unlocked by issuing the Error Reset
command. Before this command is issued, all of the
status bits required (e.g., the CRC error status) must
be read, and the last two bytes read by the DMA
discarded. The Enable Interrupt on Next Receive
Character command must be sent to the SCC so that
the next character (i.e., the First Character of the next
frame) will produce an interrupt. If this is not done, the
character will generate a DMA request, not an
interrupt.
On unlocking the Receive Buffer after the EOF
interrupt, no initialization is required with respect to the
receiver. All characters have been removed by the
DMA and the receiver is ready for the next frame.
While the Buffer is locked the SCC can receive 2 7/8
characters (8 bits/character) before there is a danger
of the receiver overrunning. The only way that this can
be specified is by referencing it to the falling edge of
the request for the last CRC byte. This time is a worst
case minimum of 33 bit-times (possibly more if there
are any characters with inserted zeros). As soon as
the Buffer is unlocked an additional 8 (minimum) bit-
times become available because the top byte of the
Buffer is freed up.
the EOF interrupt service routine has not disabled the
DMA function of the SCC, and fails to read the data
after unlocking the FIFO by issuing Error Reset
command.
UM010901-0601