Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 242
Z85C3010PSG
Manufacturer Part Number
Z85C3010PSG
Description
IC 10MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3010PSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3934
Z85C3010PSG
Z85C3010PSG
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UM010901-0601
The SDLC protocol differs from other synchronous
protocols with respect to frame timing. In Bisync mode, for
example, a host computer might temporarily interrupt
transmission by sending sync characters instead of data.
This suspended condition continues as long as the
receiver does not time out. With SDLC, however, it is
invalid to send flags in the middle of a frame to idle the line.
SYSTEM INTERFACE
The Z8002 Development Module consists of a Z8002
CPU, 16K words of dynamic RAM, 2K words of EPROM
monitor, a Z80A SIO providing dual serial ports, a
counter/timer channels, two Z80A PIO devices providing
32 programmable I/O lines, and wire wrap area for
prototyping. The block diagram is depicted in Figure 3.
Figure 2. Bit Patterns for Various Line Conditions
Figure 3. Block Diagram of Z8000 DM
Such action causes an error condition and disrupts orderly
operation. Thus, the transmitting device must send a
complete frame without interruption. If a message cannot
be transmitted completely, the primary station sends an
abort sequence and restarts the message transmission at
a later time.
Each of the peripherals in the development module is
connected in a prioritized daisy chain configuration. The
SCC is included in this configuration. The SCC is included
in this configuration by tying its IEI line to the IEO line of
another device, thus making it one step lower in interrupt
priority compared to the other device.
Using SCC with Z8000 in SDLC Protocol
Application Note
6-107
1
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