Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 107

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
Data Communication Modes
4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)
4.4.4.3 SDLC Loop Initialization
The initialization sequence for the SCC in SDLC Loop
mode is similar to the sequence used in SDLC mode, ex-
cept that it is longer. The processor should program WR4
first to select SDLC mode, and then WR10 to select the
CRC preset value and program the Mark/Flag idle bit.
The Loop Mode and Go-Active-On-Poll bits in WR10
The Loop Mode bit (D1) in WR10 is set to 1. When all of
this is complete, the transmitter is enabled by setting bit D3
of WR5 to 1. Now that the transmitter is enabled, the CRC
generator is initialized by issuing the Reset Tx CRC Gen-
erator command in WR0. The receiver is enabled by set-
ting the Go-Active-On-Poll bit (D4) in WR10 to 1. The SCC
goes on the loop when seven consecutive 1s are received,
and signals this by setting the On-Loop bit in RR10. Note
that the seven consecutive 1s will set the Break/Abort and
Hunt bits in RR0 also. Once the SCC is on the loop, the
Go-Active-On-Poll bit should be set to 0 until a message is
to be transmitted on the loop. To transmit a message on
the loop, the Go-Active-On-Poll bit should be set to 1. At
this point, the processor may either write the first character
4-32
Reg
WR4
WR3
WR5
WR7
WR6
WR15
WR7'
WR10
WR3
WR5
WR0
D7
0
d
0
0
d
1
x
x
c
r
r
D6
0
1
1
d
0
x
x
x
x
t
t
D5
1
0
x
1
x
x
1
e
0
x
0
Bit Number
D4
0
1
0
1
d
1
1
0
0
x
x
Table 4-12. SDLC Loop Mode Initialization
D3
0
1
0
1
x
x
1
1
1
0
i
D2
0
1
0
1
0
1
0
0
x
x
r
D1
0
0
1
x
x
1
1
0
0
r
r
D0
0
0
1
0
1
1
0
1
1
0
x
should not be set to 1 yet. The flag is written in WR7 and
the various options are selected in WR3 and WR5. At
this point, the other registers are initialized as necessary
(Table 4-12).
to the transmit buffer and wait for a transmit buffer empty
condition, or wait for the Break/Abort and Hunt bits to be
set in RR10 and the Loop Sending bit to be set in RR10 be-
fore writing the first data to the transmitter. The Go-Active-
On-Poll bit should be set to 0 after the transition of the
frame has begun. To go off of the loop, the processor
should set the Go-Active-On-Poll bit in WR10 to 0 and then
wait for the Loop Sending bit in RR10 to be set to 0. At this
point, the Loop Mode bit (D1) in WR10 is set to 0 to request
an orderly exit from the loop. The SCC exits SDLC Loop
mode when seven consecutive 1s have been received; at
the same time the Break/Abort and Hunt bits in RR0 are
set to 1, and the On Loop bit in RR10 is set to 0.
Description
Select x1 clock, SDLC mode, enable sync mode
rx=# of Rx bits/char, No auto enable, enter Hunt,
Enable Rx CRC, Address Search, No sync character
load inhibit
d=inverse of DTR pin, tx=# of Tx bits/char, use SDLC
CRC, r=inverse state of /RTS pin, CRC enable
SDLC Flag
Receiver secondary address
Enable access to new register
Enable extended read, Tx INT on FIFO empty,
d=REQUEST timing mode, Rx INT on 4 char, r=RTS
deactivation, auto EOM reset, auto flag tx
Enable Loop Mode, Go Active On Poll, c=CRC preset,
de=data encoding method, i=idle line
Enable Receiver
Enable Transmitter
Reset CRC generator
UM010901-0601