Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 311
Z85C3010PSG
Manufacturer Part Number
Z85C3010PSG
Description
IC 10MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3010PSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3934
Z85C3010PSG
Z85C3010PSG
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SCC™/ESCC™ User’s Manual
Zilog SCC
Q. How do you poll the external/status interupt IP bit?
A. Set the IE bits in WR15 so the conditions are latched
Q. When should the status in RR1 be checked?
A. Always read RR1 before reading the data.
Q. What conditions cause the transmit IP to be set?
A. Either the buffer is empty, or the flag after CRC is be-
Q. How do you tell if you have a Zero Count (ZC) in-
A. This bit is not latched like the other external IP bits. If
7-6
INTERRUPT CONSIDERATIONS (Continued)
terrupt?
modified vector that includes status. The vector in-
cludes the status bit (VIS, WR9) and determines which
vector register is put out on the bus during an interrupt
cycle.
and set ext/status master interrupt enable bit in WR1.
To guarantee the current status, the processor should
issue a Reset External/Status interrupts command in
WR0 to open the latches before reading the register.
For further details see the SCC Technical Manual,
section 3.4.7.
ing loaded.
an external interrupt occurs and none of the other IP
bits have changed since the last ext/status interrupt,
then the ZC condition caused it. A ZC interrupt will not
be generated if there are other ext/status (IP) pending.
The ZC stays active for each time only when the count
reached zero, approximately two PCLK time periods.
Q. How do you poll the bits in RR3A?
A. Enable interrupts in WR1 and disable MIE before polling.
Q. What happens when the SCC is programmed to in-
A. This would not be a wise thing to do. The interrupt
Q. Will IP bit (s) for external status be cleared by the
A. Yes.
terrupt on transmit buffer empty and also to re-
quest DMA activity on transmit buffer empty?
would occur but the DMA could gain control of the bus
and remove the interrupting condition before the inter-
rupt acknowledge could take place. When the CPU re-
covers control of the bus and starts the interrupt
acknowledge cycle, bus confusion results because the
peripheral no longer has a reason to interrupt.
Reset Ext/Status Interrupt?
UM010901-0601
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