EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 90
![IC CYCLONE IV FPGA 15K 169FBGA](/photos/6/73/67316/169-fbga_sml.jpg)
EP4CGX15BF14C8N
Manufacturer Part Number
EP4CGX15BF14C8N
Description
IC CYCLONE IV FPGA 15K 169FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX15BF14C8N
Number Of Logic Elements/cells
14400
Number Of Labs/clbs
900
Total Ram Bits
540000
Number Of I /o
72
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
169-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1475
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX15BF14C8N
Manufacturer:
ALTERA33
Quantity:
276
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5–28
PLL Control Signals
Clock Switchover
Cyclone IV Device Handbook, Volume 1
f
You can use the pfdena, areset, and locked signals to observe and control the PLL
operation and resynchronization.
For more information about the PLL control signals, refer to the
User
The clock switchover feature allows the PLL to switch between two reference input
clocks. Use this feature for clock redundancy or for a dual-clock domain application,
such as a system that turns on the redundant clock if the previous clock stops running.
Your design can automatically perform clock switchover when the clock is no longer
toggling, or based on the user control signal, clkswitch.
Automatic Clock Switchover
PLLs of Cyclone IV devices support a fully configurable clock switchover capability.
When the current reference clock is not present, the clock-sense block automatically
switches to the backup clock for PLL reference. The clock switchover circuit also sends
out three status signals—clkbad0, clkbad1, and activeclock—from the PLL to
implement a custom switchover circuit. You can select a clock source at the backup
clock by connecting it to the inclk1 port of the PLL in your design.
Figure 5–17
Figure 5–17. Automatic Clock Switchover Circuit
Guide.
inclk1
inclk0
shows the block diagram of the switchover circuit built into the PLL.
muxout
clksw
n Counter
Sense
Clock
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
refclk
Switchover
Machine
State
© December 2010 Altera Corporation
PFD
ALTPLL Megafunction
clkswitch
(provides manual
switchover support)
fbclk
clkbad0
clkbad1
activeclock
Hardware Features
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