EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 351

• Manufacturer Part Number: EP4CGX15BF14C8N
• Description: IC CYCLONE IV FPGA 15K 169FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX15BF14C8N

• Number Of Logic Elements/cells: 14400
• Number Of Labs/clbs: 900
• Total Ram Bits: 540000
• Number Of I /o: 72
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 169-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1475

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
SDI Mode
Table 1–24. Supported SDI Data Rates
Figure 1–68. Transceiver Channel Datapath and Clocking when Configured in SDI Mode
Note to
(1) High-speed recovered clock.
© December 2010 Altera Corporation
Note to
(1) Society of Motion Picture and Television Engineers (SMPTE).
Standard
Fabric
FPGA
tx_clkout
rx_clkout
SMPTE
292M
424M
Figure 1–68
Table
(1)
1–24:
1
:
Third-generation (3G)
High definition (HD)
Configuration
SDI mode provides the non-bonded (×1) transceiver channel datapath configuration
for HD- and 3G-SDI protocol implementations.
Cyclone IV GX transceivers configured in SDI mode provides the serialization and
deserialization functions that supports the SDI data rates as listed in
SDI functions such as scrambling/de-scrambling, framing, and cyclic redundancy
check (CRC) must be implemented in the user logic.
Figure 1–68
SDI mode.
Phase
Comp
FIFO
Rx
shows the transceiver channel datapath and clocking when configured in
wr_clk
Tx Phase
Comp
FIFO
rd_clk
Data Rate (Mbps)
Order-
Byte
ing
1483.5
1485
2967
2970
serializer
/2
Byte
De-
wr_clk
Byte Serializer
/2
Transmitter Channel PCS
Decoder
8B/10B
rd_clk
Receiver Channel PCS
Transceiver Width
FPGA Fabric-to-
Match
FIFO
20-bit
10-bit
20-bit
10-bit
20-bit
Rate
8B/10B Encoder
Deskew
FIFO
Cyclone IV Device Handbook, Volume 2
Byte SERDES Usage
Aligner
Word
Table
Not used
Not used
Used
Used
Used
low-speed recovered clock
Deserial-
1–24.
Transmitter Channel PMA
Receiver Channel PMA
izer
Serializer
(1)
1–71
CDR
low-speed clock
high-speed
clock
CDR clock