EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 254
![IC CYCLONE IV FPGA 15K 169FBGA](/photos/6/73/67316/169-fbga_sml.jpg)
EP4CGX15BF14C8N
Manufacturer Part Number
EP4CGX15BF14C8N
Description
IC CYCLONE IV FPGA 15K 169FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX15BF14C8N
Number Of Logic Elements/cells
14400
Number Of Labs/clbs
900
Total Ram Bits
540000
Number Of I /o
72
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
169-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1475
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX15BF14C8N
Manufacturer:
ALTERA33
Quantity:
276
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9–8
Accessing Error Detection Block Through User Logic
Cyclone IV Device Handbook, Volume 1
1
The error detection circuit stores the computed 32-bit CRC signature in a 32-bit
register, which is read out by user logic from the core. The cycloneiv_crcblock
primitive is a WYSIWYG component used to establish the interface from the user
logic to the error detection circuit. The cycloneiv_crcblock primitive atom
contains the input and output ports that must be included in the atom. To access the
logic array, the cycloneiv_crcblock WYSIWYG atom must be inserted into your
design.
Figure 9–3
interface that the WYSIWYG atom enables in your design.
Figure 9–3. Error Detection Block Diagram
The user logic is affected by the soft error failure, so reading out the 32-bit CRC
signature through the regout should not be relied upon to detect a soft error. You
should rely on the CRC_ERROR output signal itself, because this CRC_ERROR output
signal cannot be affected by a soft error.
To enable the cycloneiv_crcblock WYSIWYG atom, you must name the atom for
each Cyclone IV device accordingly.
80 MHz Internal Chip Oscillator
shows the error detection block diagram in FPGA devices and shows the
(Saved in the Option Register)
SRAM
Bits
Pre-Computed CRC
Computation
(1 to 256 Factor)
CRC
Clock Divider
Error Detection
Logic
Chapter 9: SEU Mitigation in Cyclone IV Devices
Logic Array
© February 2010 Altera Corporation
V
CC
(Shown in BIDIR Mode)
CRC_ERROR
Software Support
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